| mux Project Status (10/29/2012 - 17:36:51) | |||
| Project File: | a2.xise | Parser Errors: | No Errors |
| Module Name: | mux | Implementation State: | Synthesized (Failed) |
| Target Device: | xc3s100e-4vq100 |
|
|
| Product Version: | ISE 12.2 |
|
|
| Design Goal: | Balanced |
|
|
| Design Strategy: | Xilinx Default (unlocked) |
|
|
| Environment: |
|
||
| Device Utilization Summary (estimated values) | [-] | |||
| Logic Utilization | Used | Available | Utilization | |
| Number of Slices | 4 | 960 | 0% | |
| Number of 4 input LUTs | 8 | 1920 | 0% | |
| Number of bonded IOBs | 25 | 66 | 37% | |
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | Mo 29. Okt 16:45:59 2012 | ||||
| Translation Report | ||||||
| Map Report | ||||||
| Place and Route Report | ||||||
| Power Report | ||||||
| Post-PAR Static Timing Report | ||||||
| Bitgen Report | ||||||
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |