%% Der Code kompiliert zu dieser Befehlsfolge: 000000a8 : a8: 4a07 ldr r2, [pc, #28] (c8 <.text+0xc8>) * The routine pretends, all addresses are 4-Byte-aligned. Insert ". = ALIGN( 4 );" before * the definition of the PROVIDE( ... ); statement in the linker file to achieve this. * this procedure is executed in System Mode */ void Init_BSS_DATA( void ) { aa: 4908 ldr r1, [pc, #32] (cc <.text+0xcc>) ac: 4808 ldr r0, [pc, #32] (d0 <.text+0xd0>) ae: e001 b b4 b0: c908 ldmia r1!,{r3} unsigned int *dp, *sp; /* load the .data section into ram: */ dp = &_data_start; sp = &_data_load_start; while (dp < &_data_end) *dp++ = *sp++; b2: c208 stmia r2!,{r3} b4: 4282 cmp r2, r0 b6: d3fb bcc b0 %% Wenn ich nun mit Openocd das Programm flashe, starte und bei 0xa8 halte, kommt das heraus: Open On-Chip Debugger > halt requesting target halt... > Target 0 halted target halted in ARM state due to debug request, current mode: Abort cpsr: 0x600000d7 pc: 0x0000014c > soft_reset_halt requesting target halt and executing a soft reset Target 0 halted target halted in ARM state due to debug request, current mode: Supervisor cpsr: 0x600000d3 pc: 0x00000000 > bp 0xa8 2 hw > resume Target 0 resumed > Target 0 halted target halted in Thumb state due to breakpoint, current mode: System cpsr: 0x400000df pc: 0x000000a8 > step Target 0 resumed > Target 0 halted target halted in Thumb state due to single step, current mode: System cpsr: 0x400000df pc: 0x000000aa > step Target 0 resumed > Target 0 halted target halted in Thumb state due to single step, current mode: System cpsr: 0x400000df pc: 0x000000ac > step Target 0 resumed > Target 0 halted target halted in Thumb state due to single step, current mode: System cpsr: 0x400000df pc: 0x000000ae > armv4_5 reg %% Hier sieht man gut, dass r0 == r2 ist. Diese repräsentieren die zu überprüfenden Werte in der While-bedingung. r0: 00200000 r0: 00200000 r0: 00200000 r0: 00200000 r0: 00200000 r0: 00200000 r1: 00000290 r1: 00000290 r1: 00000290 r1: 00000290 r1: 00000290 r1: 00000290 r2: 00200000 r2: 00200000 r2: 00200000 r2: 00200000 r2: 00200000 r2: 00200000 r3: ffffffff r3: ffffffff r3: ffffffff r3: ffffffff r3: ffffffff r3: ffffffff r4: ffffffff r4: ffffffff r4: ffffffff r4: ffffffff r4: ffffffff r4: ffffffff r5: ffffffff r5: ffffffff r5: ffffffff r5: ffffffff r5: ffffffff r5: ffffffff r6: ffffffff r6: ffffffff r6: ffffffff r6: ffffffff r6: ffffffff r6: ffffffff r7: ffffffff r7: ffffffff r7: ffffffff r7: ffffffff r7: ffffffff r7: ffffffff r8: ffffffff r8_fiq: 00000000 r8: ffffffff r8: ffffffff r8: ffffffff r8: ffffffff r9: ffffffff r9_fiq: 00000000 r9: ffffffff r9: ffffffff r9: ffffffff r9: ffffffff r10: ffffffff r10_fiq: 00000000 r10: ffffffff r10: ffffffff r10: ffffffff r10: ffffffff r11: ffffffff r11_fiq: 00000000 r11: ffffffff r11: ffffffff r11: ffffffff r11: ffffffff r12: ffffffff r12_fiq: 00000000 r12: ffffffff r12: ffffffff r12: ffffffff r12: ffffffff r13_usr: 00203f80 r13_fiq: 00000000 r13_irq: 00000000 r13_svc: ffffffff r13_abt: 00203f80 r13_und: 00000000 lr_usr: 00000000 lr_fiq: 00000000 lr_irq: 00000000 lr_svc: ffffffff lr_abt: 00000000 lr_und: 00000000 pc: 000000ae pc: 000000ae pc: 000000ae pc: 000000ae pc: 000000ae pc: 000000ae cpsr: 400000df spsr_fiq: 00000000 spsr_irq: 00000000 spsr_svc: 00000000 spsr_abt: 600000d7 spsr_und: 00000000 > step Target 0 resumed > Target 0 halted target halted in Thumb state due to single step, current mode: System cpsr: 0x400000df pc: 0x000000b4 > step %% nun wird der CMP-Befehl ausgeführt ... Target 0 resumed > Target 0 halted target halted in Thumb state due to single step, current mode: System cpsr: 0x400000df pc: 0x000000b6 %% mit dem Ergebnis, dass das Carry-Flag gelöscht, das Zero-Flag gesetzt ist. %% und die Register sind immernoch gleich: > armv4_5 reg r0: 00200000 r0: 00200000 r0: 00200000 r0: 00200000 r0: 00200000 r0: 00200000 r1: 00000290 r1: 00000290 r1: 00000290 r1: 00000290 r1: 00000290 r1: 00000290 r2: 00200000 r2: 00200000 r2: 00200000 r2: 00200000 r2: 00200000 r2: 00200000 r3: ffffffff r3: ffffffff r3: ffffffff r3: ffffffff r3: ffffffff r3: ffffffff r4: ffffffff r4: ffffffff r4: ffffffff r4: ffffffff r4: ffffffff r4: ffffffff r5: ffffffff r5: ffffffff r5: ffffffff r5: ffffffff r5: ffffffff r5: ffffffff r6: ffffffff r6: ffffffff r6: ffffffff r6: ffffffff r6: ffffffff r6: ffffffff r7: ffffffff r7: ffffffff r7: ffffffff r7: ffffffff r7: ffffffff r7: ffffffff r8: ffffffff r8_fiq: 00000000 r8: ffffffff r8: ffffffff r8: ffffffff r8: ffffffff r9: ffffffff r9_fiq: 00000000 r9: ffffffff r9: ffffffff r9: ffffffff r9: ffffffff r10: ffffffff r10_fiq: 00000000 r10: ffffffff r10: ffffffff r10: ffffffff r10: ffffffff r11: ffffffff r11_fiq: 00000000 r11: ffffffff r11: ffffffff r11: ffffffff r11: ffffffff r12: ffffffff r12_fiq: 00000000 r12: ffffffff r12: ffffffff r12: ffffffff r12: ffffffff r13_usr: 00203f80 r13_fiq: 00000000 r13_irq: 00000000 r13_svc: ffffffff r13_abt: 00203f80 r13_und: 00000000 lr_usr: 00000000 lr_fiq: 00000000 lr_irq: 00000000 lr_svc: ffffffff lr_abt: 00000000 lr_und: 00000000 pc: 000000b6 pc: 000000b6 pc: 000000b6 pc: 000000b6 pc: 000000b6 pc: 000000b6 cpsr: 400000df spsr_fiq: 00000000 spsr_irq: 00000000 spsr_svc: 00000000 spsr_abt: 600000d7 spsr_und: 00000000 > step %% Branchinstruktion ausführen Target 0 resumed > Target 0 halted target halted in Thumb state due to single step, current mode: System cpsr: 0x400000df pc: 0x000000b0 %% wie erwartet, spring die BCC-Instruktion in die Schleife. Doch R1==R2, die while Bedingung ist also nicht erfüllt! %% Im ARM-Mode sieht der Code so aus: 000000c8 : * The routine pretends, all addresses are 4-Byte-aligned. Insert ". = ALIGN( 4 );" before * the definition of the PROVIDE( ... ); statement in the linker file to achieve this. * this procedure is executed in System Mode */ void Init_BSS_DATA( void ) { c8: e59f103c ldr r1, [pc, #60] ; 10c <.text+0x10c> cc: e59f203c ldr r2, [pc, #60] ; 110 <.text+0x110> d0: ea000001 b dc unsigned int *dp, *sp; /* load the .data section into ram: */ dp = &_data_start; sp = &_data_load_start; while (dp < &_data_end) *dp++ = *sp++; d4: e5123004 ldr r3, [r2, #-4] d8: e4813004 str r3, [r1], #4 dc: e59f3030 ldr r3, [pc, #48] ; 114 <.text+0x114> e0: e1510003 cmp r1, r3 e4: e2822004 add r2, r2, #4 ; 0x4 e8: 3afffff9 bcc d4 %% Das debugging zeigt: Open On-Chip Debugger > halt requesting target halt... > Target 0 halted target halted in ARM state due to debug request, current mode: System cpsr: 0x600000df pc: 0x000001cc > soft_reset_halt requesting target halt and executing a soft reset Target 0 halted target halted in ARM state due to debug request, current mode: Supervisor cpsr: 0x600000d3 pc: 0x00000000 > bp 0xc8 4 hw > resume Target 0 resumed > Target 0 halted target halted in ARM state due to breakpoint, current mode: System cpsr: 0x600000df pc: 0x000000c8 > step Target 0 resumed > Target 0 halted target halted in ARM state due to single step, current mode: System cpsr: 0x600000df pc: 0x000000cc > step Target 0 resumed > Target 0 halted target halted in ARM state due to single step, current mode: System cpsr: 0x600000df pc: 0x000000d0 > step Target 0 resumed > Target 0 halted target halted in ARM state due to single step, current mode: System cpsr: 0x600000df pc: 0x000000dc > step Target 0 resumed > Target 0 halted target halted in ARM state due to single step, current mode: System cpsr: 0x600000df pc: 0x000000e0 %% alle register (r1, r3 vor allem) sind mit den entsprechenden Werten geladen: > armv4_5 reg r0: 000000c8 r0: 000000c8 r0: 000000c8 r0: 000000c8 r0: 000000c8 r0: 000000c8 r1: 00200000 r1: 00200000 r1: 00200000 r1: 00200000 r1: 00200000 r1: 00200000 r2: 000002f4 r2: 000002f4 r2: 000002f4 r2: 000002f4 r2: 000002f4 r2: 000002f4 r3: 00200000 r3: 00200000 r3: 00200000 r3: 00200000 r3: 00200000 r3: 00200000 r4: ffffffff r4: ffffffff r4: ffffffff r4: ffffffff r4: ffffffff r4: ffffffff r5: ffffffff r5: ffffffff r5: ffffffff r5: ffffffff r5: ffffffff r5: ffffffff r6: ffffffff r6: ffffffff r6: ffffffff r6: ffffffff r6: ffffffff r6: ffffffff r7: ffffffff r7: ffffffff r7: ffffffff r7: ffffffff r7: ffffffff r7: ffffffff r8: ffffffff r8_fiq: 00000000 r8: ffffffff r8: ffffffff r8: ffffffff r8: ffffffff r9: ffffffff r9_fiq: 00000000 r9: ffffffff r9: ffffffff r9: ffffffff r9: ffffffff r10: ffffffff r10_fiq: 00000000 r10: ffffffff r10: ffffffff r10: ffffffff r10: ffffffff r11: ffffffff r11_fiq: 00000000 r11: ffffffff r11: ffffffff r11: ffffffff r11: ffffffff r12: ffffffff r12_fiq: 00000000 r12: ffffffff r12: ffffffff r12: ffffffff r12: ffffffff r13_usr: 00203f80 r13_fiq: 00000000 r13_irq: 00000000 r13_svc: ffffffff r13_abt: 00000000 r13_und: 00000000 lr_usr: ffffffff lr_fiq: 00000000 lr_irq: 00000000 lr_svc: ffffffff lr_abt: 00000000 lr_und: 00000000 pc: 000000e0 pc: 000000e0 pc: 000000e0 pc: 000000e0 pc: 000000e0 pc: 000000e0 cpsr: 600000df spsr_fiq: 00000000 spsr_irq: 00000000 spsr_svc: 00000000 spsr_abt: 00000000 spsr_und: 00000000 > step %% den CMP-Befehl ausführen Target 0 resumed > Target 0 halted target halted in ARM state due to single step, current mode: System cpsr: 0x600000df pc: 0x000000e4 > step Target 0 resumed > Target 0 halted target halted in ARM state due to single step, current mode: System cpsr: 0x600000df pc: 0x000000e8 > step %% den Branch-Befehl (eben nicht) ausführen. Target 0 resumed > Target 0 halted target halted in ARM state due to single step, current mode: System cpsr: 0x600000df pc: 0x000000ec %% Irgendwie sieht das für mich aus, als wenn der CMP Befehl des ARM-Mode was anderes macht als der vom Thumb-Mode. %% Hat jemand eine Erklärung parat? %% Dass es nicht an Openocd liegt, kann man leicht sehen, wenn man den Prozessor einfach so laufen lässt und anschließend unterbricht: %% er wartet - im gegensatz zum ARM-Mode - in Abort-Handler (also Zugriff auf nicht vorhandenen Speicher).