main.out: file format elf32-avr Sections: Idx Name Size VMA LMA File off Algn 0 .text 0000010a 00000000 00000000 00000094 2**0 CONTENTS, ALLOC, LOAD, READONLY, CODE 1 .data 00000000 00800060 0000010a 0000019e 2**0 CONTENTS, ALLOC, LOAD, DATA 2 .bss 00000004 00800060 00800060 0000019e 2**0 ALLOC 3 .noinit 00000000 00800064 00800064 0000019e 2**0 CONTENTS 4 .eeprom 00000000 00810000 00810000 0000019e 2**0 CONTENTS 5 .stab 0000036c 00000000 00000000 000001a0 2**2 CONTENTS, READONLY, DEBUGGING 6 .stabstr 00000084 00000000 00000000 0000050c 2**0 CONTENTS, READONLY, DEBUGGING 7 .debug_aranges 00000014 00000000 00000000 00000590 2**0 CONTENTS, READONLY, DEBUGGING 8 .debug_pubnames 00000050 00000000 00000000 000005a4 2**0 CONTENTS, READONLY, DEBUGGING 9 .debug_info 00000127 00000000 00000000 000005f4 2**0 CONTENTS, READONLY, DEBUGGING 10 .debug_abbrev 000000a1 00000000 00000000 0000071b 2**0 CONTENTS, READONLY, DEBUGGING 11 .debug_line 000000f7 00000000 00000000 000007bc 2**0 CONTENTS, READONLY, DEBUGGING 12 .debug_str 000000b3 00000000 00000000 000008b3 2**0 CONTENTS, READONLY, DEBUGGING SYMBOL TABLE: 00000000 l d .text 00000000 .text 00800060 l d .data 00000000 .data 00800060 l d .bss 00000000 .bss 00800064 l d .noinit 00000000 .noinit 00810000 l d .eeprom 00000000 .eeprom 00000000 l d .stab 00000000 .stab 00000000 l d .stabstr 00000000 .stabstr 00000000 l d .debug_aranges 00000000 .debug_aranges 00000000 l d .debug_pubnames 00000000 .debug_pubnames 00000000 l d .debug_info 00000000 .debug_info 00000000 l d .debug_abbrev 00000000 .debug_abbrev 00000000 l d .debug_line 00000000 .debug_line 00000000 l d .debug_str 00000000 .debug_str 00000000 l d *ABS* 00000000 .shstrtab 00000000 l d *ABS* 00000000 .symtab 00000000 l d *ABS* 00000000 .strtab 00000000 l df *ABS* 00000000 ../../../../../avr-libc-1.4.3/crt1/gcrt1.S 00000042 l .text 00000000 .do_copy_data_start 0000003e l .text 00000000 .do_copy_data_loop 00000052 l .text 00000000 .do_clear_bss_start 00000050 l .text 00000000 .do_clear_bss_loop 00000000 l df *ABS* 00000000 TIMER32.C 0000003f l *ABS* 00000000 __SREG__ 0000003e l *ABS* 00000000 __SP_H__ 0000003d l *ABS* 00000000 __SP_L__ 00000000 l *ABS* 00000000 __tmp_reg__ 00000001 l *ABS* 00000000 __zero_reg__ 0000005a w .text 00000000 __vector_1 0000010a g .text 00000000 _etext 000000a8 g F .text 0000001c t2_init 0000005a w .text 00000000 __vector_12 0000005a g .text 00000000 __bad_interrupt 0000010a g *ABS* 00000000 __data_load_end 0000005a w .text 00000000 __vector_6 0000005a w .text 00000000 __vector_3 0000010a g *ABS* 00000000 __data_load_start 00000026 g .text 00000000 __dtors_end 00800064 g .bss 00000000 __bss_end 0000005a w .text 00000000 __vector_11 00000026 w .text 00000000 __init 0000005a w .text 00000000 __vector_13 0000005a w .text 00000000 __vector_17 0000005a w .text 00000000 __vector_7 00000048 g .text 00000000 __do_clear_bss 00810000 g .eeprom 00000000 __eeprom_end 00000000 g .text 00000000 __vectors 00800060 g .data 00000000 __data_end 00000000 w .text 00000000 __vector_default 0000005a w .text 00000000 __vector_5 00000026 g .text 00000000 __ctors_start 00000032 g .text 00000000 __do_copy_data 00800060 g .bss 00000000 __bss_start 000000fa g F .text 00000010 main 0000005c g F .text 0000004c __vector_4 00000000 w *ABS* 00000000 __heap_end 0000005a w .text 00000000 __vector_9 0000005a w .text 00000000 __vector_2 0000005a w .text 00000000 __vector_15 000000c4 g F .text 00000036 get_ticks 00000026 g .text 00000000 __dtors_start 00000026 g .text 00000000 __ctors_end 0000045f w *ABS* 00000000 __stack 00800060 g .data 00000000 _edata 00800064 g .noinit 00000000 _end 0000005a w .text 00000000 __vector_8 00800060 g O .bss 00000004 t2_soft 0000005a w .text 00000000 __vector_14 0000005a w .text 00000000 __vector_10 0000005a w .text 00000000 __vector_16 00800060 g .data 00000000 __data_start 0000005a w .text 00000000 __vector_18 Disassembly of section .text: 00000000 <__vectors>: 0: 12 c0 rjmp .+36 ; 0x26 <__ctors_end> 2: 2b c0 rjmp .+86 ; 0x5a <__bad_interrupt> 4: 2a c0 rjmp .+84 ; 0x5a <__bad_interrupt> 6: 29 c0 rjmp .+82 ; 0x5a <__bad_interrupt> 8: 29 c0 rjmp .+82 ; 0x5c <__vector_4> a: 27 c0 rjmp .+78 ; 0x5a <__bad_interrupt> c: 26 c0 rjmp .+76 ; 0x5a <__bad_interrupt> e: 25 c0 rjmp .+74 ; 0x5a <__bad_interrupt> 10: 24 c0 rjmp .+72 ; 0x5a <__bad_interrupt> 12: 23 c0 rjmp .+70 ; 0x5a <__bad_interrupt> 14: 22 c0 rjmp .+68 ; 0x5a <__bad_interrupt> 16: 21 c0 rjmp .+66 ; 0x5a <__bad_interrupt> 18: 20 c0 rjmp .+64 ; 0x5a <__bad_interrupt> 1a: 1f c0 rjmp .+62 ; 0x5a <__bad_interrupt> 1c: 1e c0 rjmp .+60 ; 0x5a <__bad_interrupt> 1e: 1d c0 rjmp .+58 ; 0x5a <__bad_interrupt> 20: 1c c0 rjmp .+56 ; 0x5a <__bad_interrupt> 22: 1b c0 rjmp .+54 ; 0x5a <__bad_interrupt> 24: 1a c0 rjmp .+52 ; 0x5a <__bad_interrupt> 00000026 <__ctors_end>: 26: 11 24 eor r1, r1 28: 1f be out 0x3f, r1 ; 63 2a: cf e5 ldi r28, 0x5F ; 95 2c: d4 e0 ldi r29, 0x04 ; 4 2e: de bf out 0x3e, r29 ; 62 30: cd bf out 0x3d, r28 ; 61 00000032 <__do_copy_data>: 32: 10 e0 ldi r17, 0x00 ; 0 34: a0 e6 ldi r26, 0x60 ; 96 36: b0 e0 ldi r27, 0x00 ; 0 38: ea e0 ldi r30, 0x0A ; 10 3a: f1 e0 ldi r31, 0x01 ; 1 3c: 02 c0 rjmp .+4 ; 0x42 <.do_copy_data_start> 0000003e <.do_copy_data_loop>: 3e: 05 90 lpm r0, Z+ 40: 0d 92 st X+, r0 00000042 <.do_copy_data_start>: 42: a0 36 cpi r26, 0x60 ; 96 44: b1 07 cpc r27, r17 46: d9 f7 brne .-10 ; 0x3e <.do_copy_data_loop> 00000048 <__do_clear_bss>: 48: 10 e0 ldi r17, 0x00 ; 0 4a: a0 e6 ldi r26, 0x60 ; 96 4c: b0 e0 ldi r27, 0x00 ; 0 4e: 01 c0 rjmp .+2 ; 0x52 <.do_clear_bss_start> 00000050 <.do_clear_bss_loop>: 50: 1d 92 st X+, r1 00000052 <.do_clear_bss_start>: 52: a4 36 cpi r26, 0x64 ; 100 54: b1 07 cpc r27, r17 56: e1 f7 brne .-8 ; 0x50 <.do_clear_bss_loop> 58: 50 c0 rjmp .+160 ; 0xfa
0000005a <__bad_interrupt>: 5a: d2 cf rjmp .-92 ; 0x0 <__vectors> 0000005c <__vector_4>: u32 t2_soft; ISR( TIMER2_OVF_vect ) { 5c: 1f 92 push r1 5e: 0f 92 push r0 60: 0f b6 in r0, 0x3f ; 63 62: 0f 92 push r0 64: 11 24 eor r1, r1 66: 8f 93 push r24 68: 9f 93 push r25 6a: af 93 push r26 6c: bf 93 push r27 t2_soft += 256; 6e: 80 91 60 00 lds r24, 0x0060 72: 90 91 61 00 lds r25, 0x0061 76: a0 91 62 00 lds r26, 0x0062 7a: b0 91 63 00 lds r27, 0x0063 7e: 80 50 subi r24, 0x00 ; 0 80: 9f 4f sbci r25, 0xFF ; 255 82: af 4f sbci r26, 0xFF ; 255 84: bf 4f sbci r27, 0xFF ; 255 86: 80 93 60 00 sts 0x0060, r24 8a: 90 93 61 00 sts 0x0061, r25 8e: a0 93 62 00 sts 0x0062, r26 92: b0 93 63 00 sts 0x0063, r27 96: bf 91 pop r27 98: af 91 pop r26 9a: 9f 91 pop r25 9c: 8f 91 pop r24 9e: 0f 90 pop r0 a0: 0f be out 0x3f, r0 ; 63 a2: 0f 90 pop r0 a4: 1f 90 pop r1 a6: 18 95 reti 000000a8 : } void t2_init( void ) { t2_soft = 0; a8: 10 92 60 00 sts 0x0060, r1 ac: 10 92 61 00 sts 0x0061, r1 b0: 10 92 62 00 sts 0x0062, r1 b4: 10 92 63 00 sts 0x0063, r1 TCCR2 = 1<: } u32 get_ticks( void ) // read T2 as 32 bit timer { u32 val; u8 tifr; cli(); c4: f8 94 cli val = t2_soft + TCNT2; c6: 84 b5 in r24, 0x24 ; 36 c8: 20 91 60 00 lds r18, 0x0060 cc: 30 91 61 00 lds r19, 0x0061 d0: 40 91 62 00 lds r20, 0x0062 d4: 50 91 63 00 lds r21, 0x0063 d8: 28 0f add r18, r24 da: 31 1d adc r19, r1 dc: 41 1d adc r20, r1 de: 51 1d adc r21, r1 tifr = TIFR; // read interrupt flags e0: 88 b7 in r24, 0x38 ; 56 sei(); e2: 78 94 sei if( (tifr & 1< e8: 27 fd sbrc r18, 7 ea: 04 c0 rjmp .+8 ; 0xf4 val += 256; // then add overflow ec: 20 50 subi r18, 0x00 ; 0 ee: 3f 4f sbci r19, 0xFF ; 255 f0: 4f 4f sbci r20, 0xFF ; 255 f2: 5f 4f sbci r21, 0xFF ; 255 return val; } f4: ca 01 movw r24, r20 f6: b9 01 movw r22, r18 f8: 08 95 ret 000000fa
: int main( void ) { fa: cf e5 ldi r28, 0x5F ; 95 fc: d4 e0 ldi r29, 0x04 ; 4 fe: de bf out 0x3e, r29 ; 62 100: cd bf out 0x3d, r28 ; 61 u32 timerticks; t2_init(); 102: d2 df rcall .-92 ; 0xa8 sei(); 104: 78 94 sei for(;;){ timerticks = get_ticks(); 106: de df rcall .-68 ; 0xc4 108: fe cf rjmp .-4 ; 0x106