Xilinx Design Summary

FPGA Partition Summary
No partition information was found.

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	524	15,360	3%
Number of 4 input LUTs	473	15,360	3%
Logic Distribution
Number of occupied Slices	401	7,680	5%
Number of Slices containing only related logic	401	401	100%
Number of Slices containing unrelated logic	0	401	0%
Total Number 4 input LUTs	537	15,360	3%
Number used as logic	473
Number used as a route-thru	64
Number of bonded IOBs	118	173	68%
IOB Flip Flops	65
Number of GCLKs	5	8	62%
Number of DCMs	1	4	25%
Total equivalent gate count for design	15,489
Additional JTAG gate count for IOBs	5,664

Performance Summary
Final Timing Score:	93	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	1 Failing Constraint