Top Project Status (01/25/2013 - 11:21:14)
Project File: SP605.xise Parser Errors: No Errors
Module Name: Top Implementation State: Programming File Generated
Target Device: xc6slx45t-3fgg484
  • Errors:
No Errors
Product Version:ISE 14.3
  • Warnings:
7 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 29 54,576 1%  
    Number used as Flip Flops 29      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 59 27,288 1%  
    Number used as logic 58 27,288 1%  
        Number using O6 output only 25      
        Number using O5 output only 25      
        Number using O5 and O6 8      
        Number used as ROM 0      
    Number used as Memory 0 6,408 0%  
    Number used exclusively as route-thrus 1      
        Number with same-slice register load 0      
        Number with same-slice carry load 1      
        Number with other load 0      
Number of occupied Slices 17 6,822 1%  
Nummber of MUXCYs used 36 13,644 1%  
Number of LUT Flip Flop pairs used 60      
    Number with an unused Flip Flop 31 60 51%  
    Number with an unused LUT 1 60 1%  
    Number of fully used LUT-FF pairs 28 60 46%  
    Number of unique control sets 2      
    Number of slice register sites lost
        to control set restrictions
11 54,576 1%  
Number of bonded IOBs 7 296 2%  
    Number of LOCed IOBs 7 7 100%  
    Number of bonded IPADs 2 16 12%  
    Number of bonded OPADs 2 8 25%  
Number of RAMB16BWERs 0 116 0%  
Number of RAMB8BWERs 0 232 0%  
Number of BUFIO2/BUFIO2_2CLKs 0 32 0%  
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 1 16 6%  
    Number used as BUFGs 1      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 8 0%  
Number of ILOGIC2/ISERDES2s 0 376 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 376 0%  
Number of OLOGIC2/OSERDES2s 0 376 0%  
Number of BSCANs 0 4 0%  
Number of BUFHs 0 256 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 58 0%  
Number of GTPA1_DUALs 1 2 50%  
    Number of LOCed GTPA1_DUALs 1 1 100%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCIE_A1s 0 1 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 4 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 2.13      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFr 25. Jan 14:50:16 201307 Warnings (0 new)10 Infos (1 new)
Translation ReportCurrentFr 25. Jan 14:50:21 2013000
Map ReportCurrentFr 25. Jan 14:50:30 2013006 Infos (0 new)
Place and Route ReportCurrentFr 25. Jan 14:50:39 2013000
Power Report     
Post-PAR Static Timing ReportCurrentFr 25. Jan 14:50:44 2013003 Infos (0 new)
Bitgen ReportCurrentFr 25. Jan 14:50:55 2013000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentFr 25. Jan 14:50:55 2013
WebTalk Log FileCurrentFr 25. Jan 14:51:02 2013

Date Generated: 01/28/2013 - 08:18:32