Project Statistics |
PROP_Board=Spartan-6 SP605 Evaluation Platform |
PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
PROP_PropSpecInProjFile=Store all values |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
PROP_UserConstraintEditorPreference=Text Editor |
PROP_VHDLSourceAnalysisStandard=VHDL-200X |
PROP_intProjectCreationTimestamp=2013-01-22T17:03:13 |
PROP_intWbtProjectID=8F30B61D687C42D191CE26520C722E73 |
PROP_intWbtProjectIteration=109 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_lockPinsUcfFile=changed |
PROP_xilxBitgStart_IntDone=true |
PROP_xilxNgdbldMacro=changed |
PROP_xstWorkDir=changed |
PROP_AutoTop=true |
PROP_DevFamily=Spartan6 |
PROP_DevDevice=xc6slx45t |
PROP_DevFamilyPMName=spartan6 |
PROP_DevPackage=fgg484 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-3 |
PROP_PreferredLanguage=VHDL |
FILE_COREGEN=1 |
FILE_UCF=1 |
FILE_VHDL=3 |