library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

-- Portverwaltung --
entity Splitter is
	port ( 	 clk : in std_logic;
				Reset: in std_logic;
				AnzIN: in  std_logic_vector (13 downto 0);
				DISP3: out std_logic_vector (3 downto 0);
				DISP2: out std_logic_vector (3 downto 0);
				DISP1: out std_logic_vector (3 downto 0);
				DISP0: out std_logic_vector (3 downto 0));
end Splitter;

-- Hauptprogramm --
architecture Behavioral of Splitter is

signal Seg1000x: std_logic_vector (3 downto 0) := "0000";
signal Seg100x: std_logic_vector (3 downto 0) := "0000";
signal Seg10x: std_logic_vector (3 downto 0) := "0000";
signal Seg1x: std_logic_vector (3 downto 0) := "0000";

begin

DISP0 <= Seg1x;
DISP1 <= Seg10x;
DISP2 <= Seg100x;
DISP3 <= Seg1000x;

	process(clk,Reset)

variable Save : integer range 0 to 9999 := 0;
variable Wert0 : integer;
variable Wert1 : integer;
variable Wert2 : integer;
variable Wert3 : integer;
constant Teiler: integer := 10;
	begin
		if (Reset = '1') then
		elsif clk = '1' and clk'Event then
			
			Save := (conv_integer(AnzIN));
			Wert0 := (Save)MOD 10;
			Save := Save / 10;
			Wert1 := (Save)MOD 10;
			Save := Save / 10;
			Wert2 := (Save)MOD 10;
			Save := Save / 10;
			Wert3 := (Save)MOD 10;
				
		end if;

	Seg1x	 <= (conv_std_logic_vector(Wert0,4));
	Seg10x	 <= (conv_std_logic_vector(Wert1,4));
	Seg100x	 <= (conv_std_logic_vector(Wert2,4));
	Seg1000x <= (conv_std_logic_vector(Wert3,4));

	end process;
end Behavioral;