Using I/O Buffers in VHDL


library IEEE;
library APA;
use IEEE.std_logic_1164.all;

entity test is

port ( AA, BB 	: in std_logic;
       QQ 	: out std_logic);

end test;


architecture arch of test is

signal aa_s,bb_s,qq_s : std_logic;

component IB25

port (Y   :outstd_ulogic;
      PAD : in std_ulogic);
end component;

component OB25LL

port (PAD  : out std_ulogic;
      A    : in std_ulogic);
end component;


begin

u1 : IB25
port map ( PAD => AA, Y => aa_s);

u2 : IB25
port map ( PAD => BB, Y => bb_s);
qq_s <= (aa_s and bb_s);

u3 :OB25LL
port map (A =>qq_s, PAD => QQ);

end arch;