-- main.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library APA;

entity function_test is

port (clock : in std_logic;
      clk_out : out std_logic;
	  TS : out integer range 0 to 10);
end function_test;


architecture behavior of function_test is

signal clk : std_logic;
signal count: integer range 0 to 40000000;



begin

process (clock,clk) is 

variable A: integer range 0 to 11;

begin

if rising_edge(clock) then

              if count = 40000000 then
                 count  <= 0;
              else
                 count  <= count+1;
              end if;


              if count = 0 then
                 clk <= '0';                 
              elsif count = 20000000 then
                 clk <= '1';
              end if;
end if;

clk_out	<= clk;
 
if rising_edge(clk) then
   
    A:= A+1;

    if A = 10 then

        A:=0;

    end if;

    TS <= A;
   
end if;

end process;

end behavior;