-- main.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library APA;

entity function_test is

port (clock : in std_logic;
      clk_out : out std_logic;
	  TS : out std_logic_vector(0 to 10));
end function_test;


architecture behavior of function_test is

signal clk : std_logic;
signal count: integer range 0 to 65563;
signal A: integer range 0 to 12;

begin

process (clock,clk) is 

begin

if rising_edge(clock) then

    A <= 0;
              if count = 65563 then
                 count  <= 0;
              else
                 count  <= count+1;
              end if;


              if count = 0 then
                 clk <= '0';                 
              elsif count = 32768 then
                 clk <= '1';
              end if;

end if;

clk_out	<= clk;
 
if rising_edge(clk) then
   
     case A is 

        when 0 =>   TS  <=   "00000000000";
                    A <= 1;
        when 1 =>   TS  <=   "00000000001";
                    A <= 2;
        when 2 =>   TS  <=   "00000000010";
                    A <= 3;
        when 3 =>   TS  <=   "00000000100";
                    A <= 4;
        when 4 =>   TS  <=   "00000001000";
                    A <= 5;
        when 5 =>   TS  <=   "00000010000";
                    A <= 6;
        when 6 =>   TS  <=   "00000100000";
                    A <= 7;
        when 7 =>   TS  <=   "00001000000";
                    A <= 8;
        when 8 =>   TS  <=   "00010000000";
                    A <= 9;
        when 9 =>   TS  <=   "00100000000";
                    A <= 10;
        when 10 =>   TS  <=  "01000000000";
                    A <= 11;
        when 11 =>   TS  <=  "10000000000";
                    A <= 12;
        when 12 =>   TS  <=  "11111111111";
                    A <= 0;
        when others => A <= 0;

    end case;
  
  
end if;

end process;