ENTITY blafasel IS PORT ( D : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- Tristate Data-Bus WR : IN STD_LOGIC; -- WR Signal RD : IN STD_LOGIC); -- RD Signal END ENTITY blafsel; ARCHITECTURE schnipsel OF blafasel IS SIGNAL OUT_EN : BIT := '0'; SIGNAL OUT_DATA : STD_LOGIC_VECTOR( 7 DOWNTO 0) := (OTHERS => '0'); SIGNAL IN_DATA : STD_LOGIC_VECTOR( 7 DOWNTO 0) := (OTHERS => '0'); SIGNAL CFG_DATA : STD_LOGIC_VECTOR( 7 DOWNTO 0) := (OTHERS => '0'); SIGNAL X_DATA : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0'); SIGNAL Y_DATA : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0'); BEGIN -- schnipsel RD_COUNT : PROCESS(RD, RESET, X_DATA, Y_DATA) VARIABLE RD_CNT : STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); BEGIN IF RESET = '1' THEN RD_CNT := (OTHERS => '0'); ELSIF RD = '0' AND RD'event THEN IF RD_CNT /= "100" THEN RD_CNT := RD_CNT + 1; ELSE RD_CNT := "000"; END IF; END IF; IF RD = '0' THEN OUT_EN <= '1'; ELSE OUT_EN <= '0'; END IF; CASE RD_CNT IS WHEN "001" => OUT_DATA <= X_DATA(7 DOWNTO 0); WHEN "010" => OUT_DATA <= "0000" & X_DATA(11 DOWNTO 8); WHEN "011" => OUT_DATA <= Y_DATA(7 DOWNTO 0); WHEN "100" => OUT_DATA <= "0000" & Y_DATA(11 DOWNTO 8); WHEN OTHERS => OUT_DATA <= (OTHERS => '0'); END CASE; END PROCESS RD_COUNT; D <= OUT_DATA WHEN OUT_EN = '1' ELSE "ZZZZZZZZ"; READ_BUS : IN_DATA <= D; SET_CFG_REG : PROCESS(WR) BEGIN IF WR = '1' AND WR'event THEN IF OUT_EN /= '1' THEN CFG_DATA <= IN_DATA; END IF; END IF; END PROCESS SET_CFG_REG; END schnipsel;