X_SHIFT_REG: process (CLK, RESET) begin if RESET = '1' then X_DATA <= (others => '0'); elsif CLK = '0' and CLK'event then if SHIFT_EN = '1' then X_DATA <= X_DATA(10 downto 0) & ADC_SDO1; end if; end if; end process X_SHIFT_REG; Y_SHIFT_REG: process (CLK, RESET) begin if RESET = '1' then Y_DATA <= (others => '0'); elsif CLK = '0' and CLK'event then if SHIFT_EN = '1' then Y_DATA <= Y_DATA(10 downto 0) & ADC_SDO2; end if; end if; end process Y_SHIFT_REG; WRITE_ENABLE: process(RD, RESET) variable RD_CNT : STD_LOGIC_VECTOR(2 downto 0) := (others => '0'); begin if RESET = '1' then RD_CNT := (others => '0'); elsif RD = '0' and RD'event then if RD_CNT = 0 then WRITE_1_ENABLE <= '1'; WRITE_2_ENABLE <= '0'; WRITE_3_ENABLE <= '0'; WRITE_4_ENABLE <= '0'; RD_CNT := RD_CNT + 1; elsif RD_CNT = 1 then WRITE_1_ENABLE <= '0'; WRITE_2_ENABLE <= '1'; WRITE_3_ENABLE <= '0'; WRITE_4_ENABLE <= '0'; RD_CNT := RD_CNT + 1; elsif RD_CNT = 2 then WRITE_1_ENABLE <= '0'; WRITE_2_ENABLE <= '0'; WRITE_3_ENABLE <= '1'; WRITE_4_ENABLE <= '0'; RD_CNT := RD_CNT + 1; elsif RD_CNT = 3 then WRITE_1_ENABLE <= '0'; WRITE_2_ENABLE <= '0'; WRITE_3_ENABLE <= '0'; WRITE_4_ENABLE <= '1'; RD_CNT := RD_CNT + 1; end if; end if; end process WRITE_ENABLE; RD_TSBUF <= not RD and WR; READ_BUS: IN_DATA <= INOUT_DATA; INOUT_DATA <= X_DATA(7 downto 0) when WRITE_1_ENABLE = '1' else (others => 'Z'); INOUT_DATA <= ("0000" & X_DATA(11 downto 8)) when WRITE_2_ENABLE = '1' else (others => 'Z'); INOUT_DATA <= Y_DATA(7 downto 0) when WRITE_3_ENABLE = '1' else (others => 'Z'); INOUT_DATA <= ("0000" & Y_DATA(11 downto 8)) when WRITE_4_ENABLE = '1' else (others => 'Z'); SET_CFG_REG: process(RD_TSBUF, IN_DATA) begin if RD_TSBUF = '1' then CFG_DATA(7 downto 6) <= IN_DATA(7 downto 6); CFG_DATA(4 downto 0) <= IN_DATA(4 downto 0); else null; end if; end process SET_CFG_REG;