library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity main is Port ( clk : in STD_LOGIC; -- 80Mhz taster : in std_logic; -- anfang des auslesens rst : in std_logic; -- globaler reset enable : out std_logic; lad_in2 : out STD_LOGIC_VECTOR (3 downto 0); -- USB usb_RD_n : out STD_LOGIC; -- read (low active) usb_WR : inout STD_LOGIC; -- write usb_TXE_n : in STD_LOGIC; -- transmit ready (low active) usb_SIWU : out std_logic; -- send immediate / wake up usb_DATA : out STD_LOGIC_VECTOR (7 downto 0); -- usb datenbus -- Eprom eprom_clk : out STD_LOGIC; -- tackt für das eprom eprom_rst : out std_logic; -- eprom reset (low aktive) eprom_lframe : out STD_LOGIC; -- startsignal für ein frame(auslesevorgang) eprom_lad : inout STD_LOGIC_VECTOR (3 downto 0); -- bidirektionaler datenbus error : out STD_LOGIC); -- 1 wenn der eprom den datenbus nicht übernimmt, sonst 0 end main; architecture Behavioral of main is -- 1.process signal enable_1mhz : std_logic:= '0'; signal enable_count : integer range 79 downto 0:= 0; -- 2.process signal lad_in, lad_out : std_logic_vector(3 downto 0):= x"0"; signal lad_control : std_logic:= '0'; -- 3.process signal taster1 : std_logic; -- Flanke abfragen, um den Epromauslesevorgang zu starten signal state, next_state : integer range 39 downto 0:= 0; signal addr : std_logic_vector(31 downto 0):= x"00000000"; signal data : std_logic_vector(7 downto 0):= x"00"; -- hier wird 1byte des eproms zwischen gespeichert constant addr_start : std_logic_vector(31 downto 0):= x"000fffff"; constant addr_stopp : std_logic_vector(31 downto 0):= x"000e0000"; begin process(clk) -- 1. enable signal erzeugen begin if rising_edge(clk) then if enable_count = 0 then enable_1mhz <= '1'; enable_count <= 79; else enable_1mhz <= '0'; enable_count <= enable_count - 1; end if; end if; end process; process(clk) -- 2. bidirektionale verbindung für lad begin -- lad ist der eprom datenbus if rising_edge(clk) then if lad_control = '1' then eprom_lad <= lad_out; else eprom_lad <= "ZZZZ"; lad_in <= eprom_lad; end if; end if; end process; count:process(clk) -- auslesen des eproms, danach daten an usb schicken begin usb_RD_n <= '1'; usb_SIWU <= '1'; if rising_edge(clk) then usb_data <= data; if rst='1' then state <= 0; elsif enable_1mhz = '1' then -- 1MHz taster1 <= taster; state <= next_state; end if; end if; end process count; fsm: process(clk) begin if rising_edge(clk) then if rst='1' then next_state <= 0; else case state is -- State Maschine zur eprom ansteuerung when 0 => if taster1 ='0' and taster='1' then -- zum starten des auslesevorgang next_state <= 1; -- eprom_rst <='1'; -- eprom nicht mehr resetten end if;eprom_rst <= '0'; error <= '0'; lad_control <= '1'; addr <= addr_start; eprom_lframe <= '1'; eprom_clk <= '0'; usb_WR <= '0'; eprom_rst <= '0'; when 1 => eprom_clk <= '0'; next_state <= 2; eprom_rst <='1'; -- eprom nicht mehr resetten when 2 => eprom_clk <= '1'; next_state <= 3; when 3 => eprom_clk <= '0'; -- 1. clock, Start lad_control <= '1'; eprom_lframe <= '0'; lad_out <= x"0"; next_state <= 4; when 4 => eprom_clk <= '1'; next_state <= 5; when 5 => eprom_clk <= '0'; -- 2. clock, CYCTYOE + DIR eprom_lframe <= '1'; lad_out <= x"4"; -- "010x" für lesen next_state <= 6; when 6 => eprom_clk <= '1'; next_state <= 7; when 7 => eprom_clk <= '0'; -- 3. clock, Addresse 1 lad_out <= addr(31 downto 28); next_state <= 8; when 8 => eprom_clk <= '1'; next_state <= 9; when 9 => eprom_clk <= '0'; -- 4. clock, Addresse 2 lad_out <= addr(27 downto 24); next_state <= 10; when 10 => eprom_clk <= '1'; next_state <= 11; when 11 => eprom_clk <= '0'; -- 5. clock, Addresse 3 lad_out <= addr(23 downto 20); next_state <= 12; when 12 => eprom_clk <= '1'; next_state <= 13; when 13 => eprom_clk <= '0'; -- 6. clock, Addresse 4 lad_out <= addr(19 downto 16); next_state <= 14; when 14 => eprom_clk <= '1'; next_state <= 15; when 15 => eprom_clk <= '0'; -- 7. clock, Addresse 5 lad_out <= addr(15 downto 12); next_state <= 16; when 16 => eprom_clk <= '1'; next_state <= 17; when 17 => eprom_clk <= '0'; -- 8. clock, Addresse 6 lad_out <= addr(11 downto 8); next_state <= 18; when 18 => eprom_clk <= '1'; next_state <= 19; when 19 => eprom_clk <= '0'; -- 9. clock, Addresse 7 lad_out <= addr( 7 downto 4); next_state <= 20; when 20 => eprom_clk <= '1'; next_state <= 21; when 21 => eprom_clk <= '0'; -- 10. clock, Addresse 8 lad_out <= addr( 3 downto 0); next_state <= 22; when 22 => eprom_clk <= '1'; next_state <= 23; when 23 => eprom_clk <= '0'; -- 11. clock, Tar0 lad_out <= x"f"; -- signal für den eprom, das er übernimmt next_state <= 24; when 24 => eprom_clk <= '1'; next_state <= 25; when 25 => eprom_clk <= '0'; -- 12. clock, Tar1 lad_control <= '0'; -- umschalten lad datein eingang next_state <= 26; when 26 => eprom_clk <= '1'; next_state <= 27; when 27 => eprom_clk <= '0'; -- 13. clock, SYNC next_state <= 28; when 28 => eprom_clk <= '1'; -- abfrage, ob der eprom den bus übernommen hat. if lad_in = x"0" then next_state <= 29; -- wenn ja, einen schritt weiter else error <= '1'; -- wenn nein, von vorne next_state <= 1; end if; when 29 => eprom_clk <= '0'; -- 14. clock, DATA1 error <='0'; next_state <= 30; when 30 => eprom_clk <= '1'; -- 1. hälfte des Bytes data(3 downto 0) <= lad_in; next_state <= 31; when 31 => eprom_clk <= '0'; -- 15. clock, DATA2 next_state <= 32; when 32 => eprom_clk <= '1'; -- 2. hälfte des Bytes data(7 downto 4) <= lad_in; next_state <= 33; when 33 => eprom_clk <= '0'; -- 16. clock, Tar0 next_state <= 34; when 34 => eprom_clk <= '1'; next_state <= 35; when 35 => eprom_clk <= '0'; -- 17. clock, tar1 lad_control <= '1'; -- übername des busses lad_out <= x"F"; next_state <= 36; when 36 => eprom_clk <= '1'; next_state <= 37; when 37 => eprom_clk <= '0'; addr <= addr - 1; -- addresse einen runter next_state <= 38; when 38 => if usb_WR='0' and usb_TXE_n = '0' then -- write next byte if USB FIFO not full usb_WR <= '1'; next_state <= 39; end if; when 39 => usb_WR <= '0'; if addr = x"fff7ffff" then -- wenn die addresse gleich dann stop next_state <= 0; else -- wenn die adresse ungleich dann neuer durchlauf next_state <= 1; end if; when others => null; end case; end if; end if; end process fsm; enable<= enable_1mhz; lad_in2<=lad_in; end Behavioral;