Design Name | ccd_logic |
Fitting Status | Successful |
Software Version | I.27 |
Device Used | XC9572-15-PC44 |
Date | 6-14-2006, 0:51AM |
Macrocells Used | Pterms Used | Registers Used | Pins Used | Function Block Inputs Used |
---|---|---|---|---|
38/72 (53%) | 82/360 (23%) | 31/72 (44%) | 7/34 (21%) | 69/144 (48%) |
|
|
Signal mapped onto global clock net (GCK3) | /CLK |
Macrocells in high performance mode (MCHP) | 38 |
Macrocells in low power mode (MCLP) | 0 |
Total macrocells used (MC) | 38 |