-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 15:45:13 05/20/06 -- Design Name: -- Module Name: LedTests - Behavioral -- Project Name: -- Target Device: XC9536 -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity LedTests is Port ( CLOCK : in std_logic; DIRECTION : in std_logic; LED_ARRAY : out std_logic_vector(7 downto 0)); end LedTests; architecture Behavioral of LedTests is signal sCount : std_logic_vector (7 downto 0); begin process (CLOCK) begin if CLOCK='1' and CLOCK'event then if DIRECTION ='1' then sCount <= sCount + 1; else sCount <= sCount - 1; end if; end if; end process; LED_ARRAY <= sCount; end Behavioral;