// VGA Test #2 // Code ist hier konventionell sortiert module vgatest( input clk, // Beispiel arbeitet mit 25 MHz clk output hsync, output vsync, output [2:0] R, output [2:0] G, output [1:0] B ); // Definition der Register und Leitungen reg [9:0] CounterX; // 10 Bit, range 0..1023 reg [8:0] CounterY; // 9 Bit, range 0..511 reg [21:0] color; wire CounterXmaxed = (CounterX==800); wire h_enable,v_enable; wire vid_enable; // Aktionen per System-Clock always @(posedge clk) if(CounterXmaxed) CounterX <= 0; else CounterX <= CounterX + 1; if(CounterXmaxed) CounterY <= CounterY + 1; if (CounterY == 481) color <= color + 1; // Verdrahtung assign hsync = (CounterX < 659) | (CounterX > 755); assign vsync = (CounterY < 493) | (CounterY > 494); assign h_enable = (CounterX < 640); assign v_enable = (CounterY < 480); assign vid_enable = h_enable & v_enable; assign R = color[21:19] & {3{vid_enable}}; assign G = color[18:16] & {3{vid_enable}}; assign B = color[15:14] & {2{vid_enable}}; endmodule