library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity ENKODER is 
			port( 
			TASTER    : in std_logic_vector(9 downto 0);
			EINSTELL	 : in std_logic_vector(3 downto 0);
	      AUSGABE   : out std_logic_vector(3 downto 0);
			INTERRUPT : out std_logic
			);      
end ENKODER;

architecture VERHALTEN of ENKODER is
	signal TASTINT  : std_logic;
	signal EINSTINT : std_logic;
begin

AUSGABE <= 	"0000" when TASTER = "0000000000" else	-- 0 eigentlich nicht definiert
				"0000" when TASTER = "0000000001" else
				"0001" when TASTER = "0000000010" else
				"0010" when TASTER = "0000000100" else
				"0011" when TASTER = "0000001000" else
				"0100" when TASTER = "0000010000" else
				"0101" when TASTER = "0000100000" else
				"0110" when TASTER = "0001000000" else
				"0111" when TASTER = "0010000000" else
				"1000" when TASTER = "0100000000" else
				"1001" when TASTER = "1000000000";
				
				with TASTER select
TASTINT <= 	'0' when "0000000000",		 -- 0 eigentlich nicht definiert
				'1' when "0000000001",
				'1' when "0000000010",
				'1' when "0000000100",
				'1' when "0000001000",
				'1' when "0000010000",
				'1' when "0000100000",
				'1' when "0001000000",
				'1' when "0010000000",
				'1' when "0100000000",
				'1' when "1000000000",
				'0' when others;
				
				with EINSTELL select
EINSTINT <= '0' when "0000",
				'1' when "0001",
				'1' when "0010",
				'1' when "0100",
				'1' when "1000",
				'0' when others;

INTERRUPT <= TASTINT or EINSTINT;

end VERHALTEN;