# ** Warning: (vsim-8684) No drivers exist on out port /clock_spartan6_xc6s_pll_25mhz_tb/UUT/U_CORE_XIL_XC6S_DCM_20MHZ/dcm_sp_inst/STATUS(6), and its initial value is not used.
# 
# Therefore, simulation behavior may occur that is not in compliance with
# 
# the VHDL standard as the initial values come from the base signal /clock_spartan6_xc6s_pll_25mhz_tb/UUT/U_CORE_XIL_XC6S_DCM_20MHZ/status_internal(6).
# 
# ** Warning: (vsim-8684) No drivers exist on out port /clock_spartan6_xc6s_pll_25mhz_tb/UUT/U_CORE_XIL_XC6S_DCM_20MHZ/dcm_sp_inst/STATUS(4 downto 3), and its initial value is not used.
# 
# Therefore, simulation behavior may occur that is not in compliance with
# 
# the VHDL standard as the initial values come from the base signal /clock_spartan6_xc6s_pll_25mhz_tb/UUT/U_CORE_XIL_XC6S_DCM_20MHZ/status_internal(4 downto 3).