This folder has the batch files to synthesize using the XST or Synplify Pro and
implement the design through command mode or GUI mode.

Steps to run the design using the ise_flow (batch mode):

1. Executing the "ise_flow.bat" file synthesizes the design using XST or
   Synplify Pro and does the implementation of design.
   On running "ise_flow.bat" file, removes the XST/Synplify Pro report
   files first (if exist any on previous runs) and then does
   implementation of the design.

2. Running the "ise_flow.bat" file creates the ise_flow_results text file.
   It has the report file data for all the XST tool processes.

Steps to run the design using the create_ise (GUI mode - for XST cases only):

1. This file will appear for XST cases only.

2. On executing the "create_ise.bat" file creates "test.xise" project file
   and set all the properties of the design selected.

3. The design can be implemented in ISE Projnav GUI by invoking the "test.xise" project file.

4. In Linux operating systems, test.xise project can be invoked by executing the command
   'ise test.xise' from the terminal.

Other files in PAR folder :

* "MEMORY_CONTROLLER_TEST.ucf" file is the constraint file for the design. This is used by
  ISE tool during translate phase. It has clock constraints, location
  constraints, IO standards and Area group constraints if any.

* "mem_interface_top.ut" file has the options for the Configuration file
  generation i.e. the "MEMORY_CONTROLLER_TEST.bit" file to run in batch mode.

* "rem_files.bat" file has all the file names of the report files that are
  generated by ISE/Synplify Pro.

* "set_ise_prop.tcl" file has all the properties that needs to be set
  in GUI mode. This file will appear only for XST cases.

* "xst_run.txt" file has synthesis options for the XST tool.
  This file is used for batch mode.

* "icon4_cg.xco", "vio_async_in96_cg.xco", "vio_async_in100_cg.xco",
  "vio_async_in192_cg.xco" and "vio_sync_out32_cg.xco" files are used to
  generate ChipScope ila and icon EDIF/NGC files. When you want to view
  the design signals on ChipScope, you should port the design signals to
  ChipScope modules i.e., ila and icon and set DEBUG_EN parameter to 1 in
  MEMORY_CONTROLLER_TEST rtl file. In order to generate the EDIF/NGC files, you must
  execute the following commands before starting synthesis and PAR.

        coregen -b icon4_cg.xco
        coregen -b vio_async_in96_cg.xco
        coregen -b vio_async_in100_cg.xco
        coregen -b vio_async_in192_cg.xco
        coregen -b vio_sync_out32_cg.xco

Note : When you generate the design using DEBUG_EN option, the above mentioned
       ChipScope coregen commands are printed into ise_flow.bat and
       create_ise.bat files. The MEMORY_CONTROLLER_TEST rtl file will have the design
       debug signals portmapped to ila and icon ChipScope modules.

* At the start of a Chip Scope Analyzer project, all of the signals in
  every core have generic names. "MEMORY_CONTROLLER_TEST.cdc" is a file that contains
  all the signal names of all cores. Upon importing this file, signal names are
  renamed to the specified names in "MEMORY_CONTROLLER_TEST.cdc" file. This file will work
  for the generated designs from MIG. If any of the design parameter values
  are changed after generating the design, this file will not work.
  For Multiple Controller designs signal names provided in CDC file are for
  the first controller only.

Synth folder:

* Synth folder has the constraint file for Synplify Pro designs
  i.e. the "mem_interface_top_synp.sdc" file, "MEMORY_CONTROLLER_TEST.prj" file which
  has the design files to be added to the project, "script_synp.tcl" file
  that sets the synthesis options and "MEMORY_CONTROLLER_TEST.lso" file which is a custom
  library search order file for XST synthesis.

compatible_ucf folder:

* MIG outputs this folder only when Pin Compatible FPGAs are checked in GUI
  (Pin Compatible FPGAs page in GUI). It generates the UCF files for all
  the Compatible FPGAs selected in GUI. If you want to switch to any of the
  Compatible FPGAs follow the steps mentioned below.

* For example, the design is generated with component name as MEMORY_CONTROLLER_TEST with
  Target FPGA LX50t-FF1136 and Compatible FPGA LX85t-FF1136.

   - Change the FPGA name to LX85t-FF1136 from LX50t-FF1136 in ise_flow.bat,
     create_ise.bat and xst_run.txt, set_ise_prop.tcl in par folder and
     .tcl file in synth folder.
   - Paste the xc5vlx85t_ff1136.ucf file in par folder.
   - Change the UCF file name in batch file to the one in compatible_ucf
     folder i.e., change the UCF name (MEMORY_CONTROLLER_TEST.ucf) in ise_flow.bat and
     create_ise.bat file to xc5vlx85t_ff1136.ucf.
