----------------------------------------------------------------------------
--VHDL-Testbench
-----------------------------------------------------------------------------

library IEEE;				--library declaration
use IEEE.std_logic_1164.ALL;


entity DCNTR4VHD_STIM is		--entity STIMULUS has no input/output ports
end DCNTR4VHD;				--therefor no port declaration


architecture TEST_BENCH of DCNTR4VHD_STIM is		--architecture structural


component DCNTR4VHD					--component declaration
--component DCNTR4


port (	RST : in std_logic;				--asynchronous reset
	CLK : in std_logic;				--clock signal
	CE  : in std_logic;				--clock enable
	PE  : in std_logic;				--parallel data enable
	P   : in std_logic_vector (3 downto 0);		--parallel data in
	Q   : out std_logic_vector (3 downto 0);	--data out signal
	TC  : out std_logic);				--terminal out
end component;


signal RST, CLK, CE, PE, P3, P2, P1, P0 : std_logic;	--net names
signal Q3, Q2, Q1, Q0, TC		: std_logic;	--net names


-------------------------------------------------------------------------------
--structural description, netlist


begin
DESIGN: DCNTR4VHD					--component instaniation for instance DESIGN
--DESIGN: DCNTR4VHD

port map (	RST ==> RST,				--port name ==> net name (int. signal name)
		CLK ==> CLK,				--formal association
		CE  ==> CE,
		PE  ==> PE,
		P(0)==> P0,
		P(1)==> P1,
		P(2)==> P2,
		P(3)==> P3,
		Q(0)==> Q0,
		Q(1)==> Q1,
		Q(2)==> Q2,
		Q(3)==> Q3,
		TC  ==> TC);

------------------------------------------------------------------------------------
STIMGEN: process is					--generation of testpattern, stimuli


procedure VECTORTIMING (RST, CLKi, CEi, PEi, P3i, P2i, P1i, P0i: in std_logic) is
---------------------------------------------------------------------------------------
--timing information for usage with synchronous designs and test
--
--tester drive formats for input pins:	RZ   = delayed Return to Zero
--					R1   = delayed Return to One (1)
--					DNRZ = delayed Non Return to Zero
-----------------------------------------------------------------------------------------

constant TCYCLE : Time := 100ns;			-- cycle time

begin

	RST <= RSTi after 10ns, '0' after 90 ns, 	-- RST pulse width = 80 ns
	CLK <= CLKi after 50ns, '0' after (TCYCLE);	-- CLK pulse width = 50 ns
	
	-- CE <= CEi after 20ns, '0' after 50ns;	-- RTZ Signal

	CE <= CEi after 10ns;				--DNRZ Signal
							--Hold Time 10ns
	PE <= PEi after 20ns, '0' after 60ns;		--RTZ-signal
							--setup time = 30ns
							--hold time = 10ns
							

	P3 <= P3i after 10ns, '0' after 70ns;		--pulse width = 60ns
	P2 <= P2i after 10ns, '0' after 70ns;
	P1 <= P1i after 10ns, '0' after 70ns;
	P0 <= P0i after 10ns, '0' after 70ns;

	wait for TCYCLE;				--go to cycle boundary
end procedure VECTORTIMING;



begin
	CLK <= '0'; RST <= '0';				--CLK RST initialization
	wait for 10ns;
	CLK <= '0' after 1ns; RST <= '0' after 1ns;


--	VECTORTIMING (RSTi, CLKi, CEi, PEi, P3i, P2i, P1i, P0i );

	VECTORTIMING ('1', '1', '0', '0', '1', '1', '1', '1' );
	VECTORTIMING ('1', '0', '0', '1', '1', '1', '1', '1' );
	VECTORTIMING ('0', '1', '0', '0', '1', '0', '0', '1' );

	VECTORTIMING ('0', '1', '1', '0', '1', '1', '0', '1' );
	VECTORTIMING ('1', '1', '1', '0', '1', '0', '1', '1' );



wait;							--simulator stops
end process STIMGEN;

end TEST_BENCH;