//----------------------------------------------------------------------- // save osc1+2 values // osc1_temp = 20 osc2_temp = 21 mov osc1_temp, chanalA_0 mov osc2_temp, chanalB_0 //----------------------------------------------------------------------- // osc1 level // LDS R18, osc1_value1 MUL R18, osc1_temp ; mul R18*temp_osc1 result in R0+R1 MOVW R18, R0 ; result in r0/r1 mov to r18/r19 // div 127 ANDI R18, 0xF0 ; clr Low-Nibble from R18 SWAP R18 ; SWAP High-Nibble to Low-Nibble LSR R18 ; 3x shift right LSR R18 LSR R18 LSL R19 ; R19 1x shift left ADD R18, R19 ; ADD R18+R19 // set osc1 value to chanal_A mov chanalA_0,R18 mov chanalA_1,R19 //----------------------------------------------------------------------- // osc1 balance // LDS R18, osc1_value2 MUL R18, osc1_temp MOVW R18, R0 // div 127 ANDI R18, 0xF0 ; clr Low-Nibble from R18 SWAP R18 ; SWAP High-Nibble to Low-Nibble LSR R18 ; 3x shift right LSR R18 LSR R18 LSL R19 ; R19 1x shift left ADD R18, R19 ; ADD R18+R19 // set osc1 balance value to chanal_B mov chanalB_0,R18 mov chanalB_1,R19 //----------------------------------------------------------------------- // osc2 level // LDS R18, osc2_value1 MUL R18, osc2_temp ; mul R18+R19 result in R0+R1 MOVW R18, R0 ; move result to r18+r19 // div 127 ANDI R18, 0xF0 ; clr Low-Nibble from R18 SWAP R18 ; SWAP High-Nibble to Low-Nibble LSR R18 ; 3x shift right LSR R18 LSR R18 LSL R19 ; R19 1x shift left ADD R18, R19 ; ADD R18+R19 // set osc2 value to chanal_A ADD chanalA_0,R18 ADC chanalA_1,R19 //----------------------------------------------------------------------- // osc2 balance // LDS R18, osc2_value2 MUL R18, osc2_temp MOVW R18, R0 // div 127 ANDI R18, 0xF0 ; clr Low-Nibble from R18 SWAP R18 ; SWAP High-Nibble to Low-Nibble LSR R18 ; 3x shift right LSR R18 LSR R18 LSL R19 ; R19 1x shift left ADD R18, R19 ; ADD R18+R19 // set oc2 balance to chanal_B ADD chanalB_0,R18 ADC chanalB_1,R19 //=============================================================== // noise generator //=============================================================== noise_gen: LDS PhaseA0, noise+0 ; load noise register LDS PhaseA1, noise+1 ; LDS PhaseA2, noise+2 ; BST PhaseA0, 4 ; Bit 4 (0:4) laden BLD R30, 0 ; BST PhaseA2, 7 ; Bit 23 (2:7) laden BLD R31, 0 ; EOR R30, R31 ; XOR der beiden Bits ROR R30 ; in Carry shiften ROL PhaseA0 ; Buffer links schieben mit Carry ROL PhaseA1 ; ROL PhaseA2 ; STS noise+0, PhaseA0 ; save noise register STS noise+1, PhaseA1 ; STS noise+2, PhaseA2 ; // set noise level left and balance temp_noise = 20 ; temp-register R20 MOV temp_noise, PhaseA1 ; save noise to R20 LDS R18, noise_value1 MUL R18, temp_noise ; mul R18+R19 result in R0+R1 MOVW R18, R0 ; move result to r18+r19 // div 127 ANDI R18, 0xF0 ; clr Low-Nibble from R18 SWAP R18 ; SWAP High-Nibble to Low-Nibble LSR R18 ; 3x shift right LSR R18 LSR R18 LSL R19 ; R19 1x shift left ADD R18, R19 ; ADD R18+R19 // add noise chanal_A ADD chanalA_0,R18 ADC chanalA_1,R19 // set noise lefel right and balance LDS R18, noise_value2 MOV R19, temp_noise ; load noise MUL R18, R19 MOVW R18, R0 // div 127 ANDI R18, 0xF0 ; clr Low-Nibble from R18 SWAP R18 ; SWAP High-Nibble to Low-Nibble LSR R18 ; 3x shift right LSR R18 LSR R18 LSL R19 ; R19 1x shift left ADD R18, R19 ; ADD R18+R19 // add noise chanal_B ADD chanalB_0,R18 ADC chanalB_1,R19 //----------------------------------------------------------------------- // Chanal Output chan_out: // convert Chanal_A to 12Bit LSL chanalA_0 ROL chanalA_1 LSL chanalA_0 ROL chanalA_1 LSL chanalA_0 ROL chanalA_1 // convert Chanal_B to 12Bit LSL chanalB_0 ROL chanalB_1 LSL chanalB_0 ROL chanalB_1 LSL chanalB_0 ROL chanalB_1 // send chanal_A value to DACA STS 0x0318, chanalA_0 ; 2 L-Byte to DAC-Register DACAL STS 0x0319, chanalA_1 ; 2 H-Byte to DAC Register DACAH // send chanal_B value to DACB STS 0x0338, chanalB_0 ; 2 L-Byte to DAC-Register DACBL STS 0x0339, chanalB_1 ; 2 H-Byte to DAC Register DAcBH