| PMP Project Status (09/23/2013 - 21:51:16) | |||
| Project File: | AFE.xise | Parser Errors: | No Errors |
| Module Name: | PMP | Implementation State: | Translated |
| Target Device: | xc6slx45-2csg324 |
|
|
| Product Version: | ISE 14.5 |
|
|
| Design Goal: | Balanced |
|
|
| Design Strategy: | Xilinx Default (unlocked) |
|
|
| Environment: |
|
||
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | ||||||
| Translation Report | ||||||
| Map Report | ||||||
| Place and Route Report | ||||||
| CPLD Fitter Report (Text) | ||||||
| Power Report | ||||||
| Post-PAR Static Timing Report | ||||||
| Bitgen Report | ||||||
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| ISIM Simulator Log | Out of Date | Mo 23. Sep 21:50:02 2013 | |