library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity IO_mux is Generic ( width : integer := 8); Port ( data_bus : inout std_logic_vector(7 downto 0); adr_bus : in std_logic_vector(3 downto 0); rd : in std_logic; wr : in std_logic; cs : in std_logic); end IO_mux; architecture Behavioral of IO_mux is type reg_file is array(15 downto 0) of std_logic_vector(width-1 downto 0); signal my_reg : reg_file; signal read_bus : std_logic_vector(width-1 downto 0); signal adr_int : integer; begin adr_int <= conv_integer(adr_bus); -- IO read mux data_bus <= read_bus when rd = '0' and cs = '0' else (others=>'Z'); -- register write access process(wr) begin if rising_edge(wr) then if cs='0' then my_reg(adr_int) <= data_bus; end if; end if; end process; -- register read access process(wr) begin case adr_int is when 0 => read_bus <= my_reg(0); when 1 => read_bus <= my_reg(1); when 2 => read_bus <= my_reg(2); when 3 => read_bus <= my_reg(3); when 4 => read_bus <= my_reg(4); when 5 => read_bus <= my_reg(5); when 6 => read_bus <= my_reg(6); when 7 => read_bus <= my_reg(7); when 8 => read_bus <= my_reg(8); when 9 => read_bus <= my_reg(9); when 10 => read_bus <= my_reg(10); when 11 => read_bus <= my_reg(11); when 12 => read_bus <= my_reg(12); when 13 => read_bus <= my_reg(13); when 14 => read_bus <= my_reg(14); when 15 => read_bus <= my_reg(15); when others => read_bus <= (others=>'0'); end case; end process; end Behavioral;