Static Timing Analysis

Project : LIN_Slave_Example01
Build Time : 10/23/13 09:35:32
Device : CY8C3866AXI-040
Temperature : -40C - 85/125C
Vdda : 5.00
Vddd : 5.00
Vio0 : 5.00
Vio1 : 5.00
Vio2 : 5.00
Vio3 : 5.00
Voltage : 5.0
Vusb : 5.00
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 12.000 MHz 12.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 60.000 MHz 60.000 MHz N/A
LINS_IntClk CyMASTER_CLK 153.453 kHz 153.453 kHz 53.183 MHz
CyBUS_CLK CyMASTER_CLK 60.000 MHz 60.000 MHz 83.188 MHz
CyPLL_OUT CyPLL_OUT 60.000 MHz 60.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 16.6667ns(60 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
L_RXD_1(0)_SYNC/out \LINS:bLIN:StsReg\/status_1 83.188 MHz 12.021 4.646
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,1) 1 L_RXD_1(0)_SYNC L_RXD_1(0)_SYNC/clock L_RXD_1(0)_SYNC/out 1.480
Route 1 Net_39_SYNCOUT L_RXD_1(0)_SYNC/out \LINS:bLIN:edge_detect\/main_1 3.364
macrocell30 U(0,0) 1 \LINS:bLIN:edge_detect\ \LINS:bLIN:edge_detect\/main_1 \LINS:bLIN:edge_detect\/q 3.350
Route 1 \LINS:bLIN:edge_detect\ \LINS:bLIN:edge_detect\/q \LINS:bLIN:StsReg\/status_1 2.257
statusicell3 U(0,0) 1 \LINS:bLIN:StsReg\ SETUP 1.570
Clock Skew 0.000
L_RXD_1(0)_SYNC/out \LINS:bLIN:state_2\/main_6 107.956 MHz 9.263 7.404
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,1) 1 L_RXD_1(0)_SYNC L_RXD_1(0)_SYNC/clock L_RXD_1(0)_SYNC/out 1.480
Route 1 Net_39_SYNCOUT L_RXD_1(0)_SYNC/out \LINS:bLIN:state_2\/main_6 4.273
macrocell41 U(0,3) 1 \LINS:bLIN:state_2\ SETUP 3.510
Clock Skew 0.000
L_RXD_1(0)_SYNC/out \LINS:bLIN:inact_state_0\/main_5 119.489 MHz 8.369 8.298
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,1) 1 L_RXD_1(0)_SYNC L_RXD_1(0)_SYNC/clock L_RXD_1(0)_SYNC/out 1.480
Route 1 Net_39_SYNCOUT L_RXD_1(0)_SYNC/out \LINS:bLIN:inact_state_0\/main_5 3.379
macrocell34 U(0,0) 1 \LINS:bLIN:inact_state_0\ SETUP 3.510
Clock Skew 0.000
L_RXD_1(0)_SYNC/out \LINS:bLIN:inact_state_1\/main_6 119.489 MHz 8.369 8.298
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,1) 1 L_RXD_1(0)_SYNC L_RXD_1(0)_SYNC/clock L_RXD_1(0)_SYNC/out 1.480
Route 1 Net_39_SYNCOUT L_RXD_1(0)_SYNC/out \LINS:bLIN:inact_state_1\/main_6 3.379
macrocell35 U(0,0) 1 \LINS:bLIN:inact_state_1\ SETUP 3.510
Clock Skew 0.000
L_RXD_1(0)_SYNC/out \LINS:bLIN:inact_state_2\/main_5 119.489 MHz 8.369 8.298
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,1) 1 L_RXD_1(0)_SYNC L_RXD_1(0)_SYNC/clock L_RXD_1(0)_SYNC/out 1.480
Route 1 Net_39_SYNCOUT L_RXD_1(0)_SYNC/out \LINS:bLIN:inact_state_2\/main_5 3.379
macrocell36 U(0,0) 1 \LINS:bLIN:inact_state_2\ SETUP 3.510
Clock Skew 0.000
L_RXD_1(0)_SYNC/out \LINS:bLIN:state_0\/main_6 119.589 MHz 8.362 8.305
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,1) 1 L_RXD_1(0)_SYNC L_RXD_1(0)_SYNC/clock L_RXD_1(0)_SYNC/out 1.480
Route 1 Net_39_SYNCOUT L_RXD_1(0)_SYNC/out \LINS:bLIN:state_0\/main_6 3.372
macrocell39 U(0,2) 1 \LINS:bLIN:state_0\ SETUP 3.510
Clock Skew 0.000
L_RXD_1(0)_SYNC/out \LINS:Net_630\/main_1 119.703 MHz 8.354 8.313
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,1) 1 L_RXD_1(0)_SYNC L_RXD_1(0)_SYNC/clock L_RXD_1(0)_SYNC/out 1.480
Route 1 Net_39_SYNCOUT L_RXD_1(0)_SYNC/out \LINS:Net_630\/main_1 3.364
macrocell3 U(0,0) 1 \LINS:Net_630\ SETUP 3.510
Clock Skew 0.000
L_RXD_1(0)_SYNC/out \LINS:bLIN:rxd_reg\/main_0 119.703 MHz 8.354 8.313
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,1) 1 L_RXD_1(0)_SYNC L_RXD_1(0)_SYNC/clock L_RXD_1(0)_SYNC/out 1.480
Route 1 Net_39_SYNCOUT L_RXD_1(0)_SYNC/out \LINS:bLIN:rxd_reg\/main_0 3.364
macrocell38 U(0,0) 1 \LINS:bLIN:rxd_reg\ SETUP 3.510
Clock Skew 0.000
L_RXD_1(0)_SYNC/out \LINS:bLIN:state_1\/main_6 119.775 MHz 8.349 8.318
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,1) 1 L_RXD_1(0)_SYNC L_RXD_1(0)_SYNC/clock L_RXD_1(0)_SYNC/out 1.480
Route 1 Net_39_SYNCOUT L_RXD_1(0)_SYNC/out \LINS:bLIN:state_1\/main_6 3.359
macrocell40 U(0,2) 1 \LINS:bLIN:state_1\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 6516.67ns(153.453 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\LINS:UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \LINS:UART:BUART:sTX:TxSts\/status_0 53.183 MHz 18.803 6497.864
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,3) 1 \LINS:UART:BUART:sTX:TxShifter:u0\ \LINS:UART:BUART:sTX:TxShifter:u0\/clock \LINS:UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \LINS:UART:BUART:tx_fifo_empty\ \LINS:UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \LINS:UART:BUART:tx_status_0\/main_2 4.444
macrocell25 U(1,3) 1 \LINS:UART:BUART:tx_status_0\ \LINS:UART:BUART:tx_status_0\/main_2 \LINS:UART:BUART:tx_status_0\/q 3.350
Route 1 \LINS:UART:BUART:tx_status_0\ \LINS:UART:BUART:tx_status_0\/q \LINS:UART:BUART:sTX:TxSts\/status_0 4.159
statusicell2 U(1,3) 1 \LINS:UART:BUART:sTX:TxSts\ SETUP 1.570
Clock Skew 0.000
\LINS:UART:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \LINS:UART:BUART:sRX:RxSts\/status_4 54.171 MHz 18.460 6498.207
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,1) 1 \LINS:UART:BUART:sRX:RxShifter:u0\ \LINS:UART:BUART:sRX:RxShifter:u0\/clock \LINS:UART:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \LINS:UART:BUART:rx_fifofull\ \LINS:UART:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \LINS:UART:BUART:rx_status_4\/main_1 2.303
macrocell18 U(1,1) 1 \LINS:UART:BUART:rx_status_4\ \LINS:UART:BUART:rx_status_4\/main_1 \LINS:UART:BUART:rx_status_4\/q 3.350
Route 1 \LINS:UART:BUART:rx_status_4\ \LINS:UART:BUART:rx_status_4\/q \LINS:UART:BUART:sRX:RxSts\/status_4 5.957
statusicell1 U(1,2) 1 \LINS:UART:BUART:sRX:RxSts\ SETUP 1.570
Clock Skew 0.000
\LINS:bLIN:inact_state_2\/q \LINS:bLIN:InactFSM:BusInactDp:u0\/cs_addr_2 55.185 MHz 18.121 6498.546
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell36 U(0,0) 1 \LINS:bLIN:inact_state_2\ \LINS:bLIN:inact_state_2\/clock_0 \LINS:bLIN:inact_state_2\/q 1.250
Route 1 \LINS:bLIN:inact_state_2\ \LINS:bLIN:inact_state_2\/q \LINS:bLIN:InactFSM:BusInactDp:u0\/cs_addr_2 5.341
datapathcell3 U(0,0) 1 \LINS:bLIN:InactFSM:BusInactDp:u0\ SETUP 11.530
Clock Skew 0.000
\LINS:bLIN:LINDp:u0\/ce0_comb \LINS:bLIN:StsReg\/status_0 55.203 MHz 18.115 6498.552
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(0,2) 1 \LINS:bLIN:LINDp:u0\ \LINS:bLIN:LINDp:u0\/clock \LINS:bLIN:LINDp:u0\/ce0_comb 5.060
Route 1 \LINS:bLIN:cmp_a0_d0\ \LINS:bLIN:LINDp:u0\/ce0_comb \LINS:bLIN:break_pulse\/main_3 2.302
macrocell29 U(0,2) 1 \LINS:bLIN:break_pulse\ \LINS:bLIN:break_pulse\/main_3 \LINS:bLIN:break_pulse\/q 3.350
Route 1 \LINS:bLIN:break_pulse\ \LINS:bLIN:break_pulse\/q \LINS:bLIN:StsReg\/status_0 5.833
statusicell3 U(0,0) 1 \LINS:bLIN:StsReg\ SETUP 1.570
Clock Skew 0.000
\LINS:Net_630\/q \LINS:UART:BUART:sRX:RxShifter:u0\/route_si 58.248 MHz 17.168 6499.499
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(0,0) 1 \LINS:Net_630\ \LINS:Net_630\/clock_0 \LINS:Net_630\/q 1.250
Route 1 \LINS:Net_630\ \LINS:Net_630\/q \LINS:UART:BUART:rx_postpoll\/main_1 5.052
macrocell12 U(0,1) 1 \LINS:UART:BUART:rx_postpoll\ \LINS:UART:BUART:rx_postpoll\/main_1 \LINS:UART:BUART:rx_postpoll\/q 3.350
Route 1 \LINS:UART:BUART:rx_postpoll\ \LINS:UART:BUART:rx_postpoll\/q \LINS:UART:BUART:sRX:RxShifter:u0\/route_si 2.306
datapathcell1 U(1,1) 1 \LINS:UART:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
\LINS:bLIN:state_2\/q \LINS:bLIN:LINDp:u0\/cs_addr_2 58.579 MHz 17.071 6499.596
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell41 U(0,3) 1 \LINS:bLIN:state_2\ \LINS:bLIN:state_2\/clock_0 \LINS:bLIN:state_2\/q 1.250
Route 1 \LINS:bLIN:state_2\ \LINS:bLIN:state_2\/q \LINS:bLIN:LINDp:u0\/cs_addr_2 4.291
datapathcell4 U(0,2) 1 \LINS:bLIN:LINDp:u0\ SETUP 11.530
Clock Skew 0.000
\LINS:UART:BUART:sTX:sCLOCK:TxBitCounter\/count_0 \LINS:UART:BUART:sTX:TxShifter:u0\/cs_addr_0 58.882 MHz 16.983 6499.684
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,2) 1 \LINS:UART:BUART:sTX:sCLOCK:TxBitCounter\ \LINS:UART:BUART:sTX:sCLOCK:TxBitCounter\/clock \LINS:UART:BUART:sTX:sCLOCK:TxBitCounter\/count_0 2.110
Route 1 \LINS:UART:BUART:txbitcount_0\ \LINS:UART:BUART:sTX:sCLOCK:TxBitCounter\/count_0 \LINS:UART:BUART:tx_bitclk_enable_pre\/main_2 2.321
macrocell21 U(1,2) 1 \LINS:UART:BUART:tx_bitclk_enable_pre\ \LINS:UART:BUART:tx_bitclk_enable_pre\/main_2 \LINS:UART:BUART:tx_bitclk_enable_pre\/q 3.350
Route 1 \LINS:UART:BUART:tx_bitclk_enable_pre\ \LINS:UART:BUART:tx_bitclk_enable_pre\/q \LINS:UART:BUART:sTX:TxShifter:u0\/cs_addr_0 2.912
datapathcell2 U(1,3) 1 \LINS:UART:BUART:sTX:TxShifter:u0\ SETUP 6.290
Clock Skew 0.000
\LINS:UART:BUART:sTX:sCLOCK:TxBitCounter\/count_1 \LINS:UART:BUART:sTX:TxShifter:u0\/cs_addr_0 58.896 MHz 16.979 6499.688
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,2) 1 \LINS:UART:BUART:sTX:sCLOCK:TxBitCounter\ \LINS:UART:BUART:sTX:sCLOCK:TxBitCounter\/clock \LINS:UART:BUART:sTX:sCLOCK:TxBitCounter\/count_1 2.110
Route 1 \LINS:UART:BUART:txbitcount_1\ \LINS:UART:BUART:sTX:sCLOCK:TxBitCounter\/count_1 \LINS:UART:BUART:tx_bitclk_enable_pre\/main_1 2.317
macrocell21 U(1,2) 1 \LINS:UART:BUART:tx_bitclk_enable_pre\ \LINS:UART:BUART:tx_bitclk_enable_pre\/main_1 \LINS:UART:BUART:tx_bitclk_enable_pre\/q 3.350
Route 1 \LINS:UART:BUART:tx_bitclk_enable_pre\ \LINS:UART:BUART:tx_bitclk_enable_pre\/q \LINS:UART:BUART:sTX:TxShifter:u0\/cs_addr_0 2.912
datapathcell2 U(1,3) 1 \LINS:UART:BUART:sTX:TxShifter:u0\ SETUP 6.290
Clock Skew 0.000
\LINS:UART:BUART:sTX:sCLOCK:TxBitCounter\/count_2 \LINS:UART:BUART:sTX:TxShifter:u0\/cs_addr_0 58.900 MHz 16.978 6499.689
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,2) 1 \LINS:UART:BUART:sTX:sCLOCK:TxBitCounter\ \LINS:UART:BUART:sTX:sCLOCK:TxBitCounter\/clock \LINS:UART:BUART:sTX:sCLOCK:TxBitCounter\/count_2 2.110
Route 1 \LINS:UART:BUART:txbitcount_2\ \LINS:UART:BUART:sTX:sCLOCK:TxBitCounter\/count_2 \LINS:UART:BUART:tx_bitclk_enable_pre\/main_0 2.316
macrocell21 U(1,2) 1 \LINS:UART:BUART:tx_bitclk_enable_pre\ \LINS:UART:BUART:tx_bitclk_enable_pre\/main_0 \LINS:UART:BUART:tx_bitclk_enable_pre\/q 3.350
Route 1 \LINS:UART:BUART:tx_bitclk_enable_pre\ \LINS:UART:BUART:tx_bitclk_enable_pre\/q \LINS:UART:BUART:sTX:TxShifter:u0\/cs_addr_0 2.912
datapathcell2 U(1,3) 1 \LINS:UART:BUART:sTX:TxShifter:u0\ SETUP 6.290
Clock Skew 0.000
\LINS:bLIN:inact_state_0\/q \LINS:bLIN:InactFSM:BusInactDp:u0\/cs_addr_0 60.485 MHz 16.533 6500.134
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell34 U(0,0) 1 \LINS:bLIN:inact_state_0\ \LINS:bLIN:inact_state_0\/clock_0 \LINS:bLIN:inact_state_0\/q 1.250
Route 1 \LINS:bLIN:inact_state_0\ \LINS:bLIN:inact_state_0\/q \LINS:bLIN:InactFSM:BusInactDp:u0\/cs_addr_0 3.753
datapathcell3 U(0,0) 1 \LINS:bLIN:InactFSM:BusInactDp:u0\ SETUP 11.530
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
L_RXD_1(0)_SYNC/out \LINS:bLIN:state_1\/main_6 4.359
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,1) 1 L_RXD_1(0)_SYNC L_RXD_1(0)_SYNC/clock L_RXD_1(0)_SYNC/out 1.000
Route 1 Net_39_SYNCOUT L_RXD_1(0)_SYNC/out \LINS:bLIN:state_1\/main_6 3.359
macrocell40 U(0,2) 1 \LINS:bLIN:state_1\ HOLD 0.000
Clock Skew 0.000
L_RXD_1(0)_SYNC/out \LINS:Net_630\/main_1 4.364
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,1) 1 L_RXD_1(0)_SYNC L_RXD_1(0)_SYNC/clock L_RXD_1(0)_SYNC/out 1.000
Route 1 Net_39_SYNCOUT L_RXD_1(0)_SYNC/out \LINS:Net_630\/main_1 3.364
macrocell3 U(0,0) 1 \LINS:Net_630\ HOLD 0.000
Clock Skew 0.000
L_RXD_1(0)_SYNC/out \LINS:bLIN:rxd_reg\/main_0 4.364
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,1) 1 L_RXD_1(0)_SYNC L_RXD_1(0)_SYNC/clock L_RXD_1(0)_SYNC/out 1.000
Route 1 Net_39_SYNCOUT L_RXD_1(0)_SYNC/out \LINS:bLIN:rxd_reg\/main_0 3.364
macrocell38 U(0,0) 1 \LINS:bLIN:rxd_reg\ HOLD 0.000
Clock Skew 0.000
L_RXD_1(0)_SYNC/out \LINS:bLIN:state_0\/main_6 4.372
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,1) 1 L_RXD_1(0)_SYNC L_RXD_1(0)_SYNC/clock L_RXD_1(0)_SYNC/out 1.000
Route 1 Net_39_SYNCOUT L_RXD_1(0)_SYNC/out \LINS:bLIN:state_0\/main_6 3.372
macrocell39 U(0,2) 1 \LINS:bLIN:state_0\ HOLD 0.000
Clock Skew 0.000
L_RXD_1(0)_SYNC/out \LINS:bLIN:inact_state_0\/main_5 4.379
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,1) 1 L_RXD_1(0)_SYNC L_RXD_1(0)_SYNC/clock L_RXD_1(0)_SYNC/out 1.000
Route 1 Net_39_SYNCOUT L_RXD_1(0)_SYNC/out \LINS:bLIN:inact_state_0\/main_5 3.379
macrocell34 U(0,0) 1 \LINS:bLIN:inact_state_0\ HOLD 0.000
Clock Skew 0.000
L_RXD_1(0)_SYNC/out \LINS:bLIN:inact_state_1\/main_6 4.379
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,1) 1 L_RXD_1(0)_SYNC L_RXD_1(0)_SYNC/clock L_RXD_1(0)_SYNC/out 1.000
Route 1 Net_39_SYNCOUT L_RXD_1(0)_SYNC/out \LINS:bLIN:inact_state_1\/main_6 3.379
macrocell35 U(0,0) 1 \LINS:bLIN:inact_state_1\ HOLD 0.000
Clock Skew 0.000
L_RXD_1(0)_SYNC/out \LINS:bLIN:inact_state_2\/main_5 4.379
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,1) 1 L_RXD_1(0)_SYNC L_RXD_1(0)_SYNC/clock L_RXD_1(0)_SYNC/out 1.000
Route 1 Net_39_SYNCOUT L_RXD_1(0)_SYNC/out \LINS:bLIN:inact_state_2\/main_5 3.379
macrocell36 U(0,0) 1 \LINS:bLIN:inact_state_2\ HOLD 0.000
Clock Skew 0.000
L_RXD_1(0)_SYNC/out \LINS:bLIN:state_2\/main_6 5.273
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,1) 1 L_RXD_1(0)_SYNC L_RXD_1(0)_SYNC/clock L_RXD_1(0)_SYNC/out 1.000
Route 1 Net_39_SYNCOUT L_RXD_1(0)_SYNC/out \LINS:bLIN:state_2\/main_6 4.273
macrocell41 U(0,3) 1 \LINS:bLIN:state_2\ HOLD 0.000
Clock Skew 0.000
L_RXD_1(0)_SYNC/out \LINS:bLIN:StsReg\/status_1 7.971
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,1) 1 L_RXD_1(0)_SYNC L_RXD_1(0)_SYNC/clock L_RXD_1(0)_SYNC/out 1.000
Route 1 Net_39_SYNCOUT L_RXD_1(0)_SYNC/out \LINS:bLIN:edge_detect\/main_1 3.364
macrocell30 U(0,0) 1 \LINS:bLIN:edge_detect\ \LINS:bLIN:edge_detect\/main_1 \LINS:bLIN:edge_detect\/q 3.350
Route 1 \LINS:bLIN:edge_detect\ \LINS:bLIN:edge_detect\/q \LINS:bLIN:StsReg\/status_1 2.257
statusicell3 U(0,0) 1 \LINS:bLIN:StsReg\ HOLD -2.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\LINS:Net_630\/q \LINS:UART:BUART:rx_state_2\/main_8 3.484
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(0,0) 1 \LINS:Net_630\ \LINS:Net_630\/clock_0 \LINS:Net_630\/q 1.250
Route 1 \LINS:Net_630\ \LINS:Net_630\/q \LINS:UART:BUART:rx_state_2\/main_8 2.234
macrocell14 U(1,0) 1 \LINS:UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\LINS:UART:BUART:rx_state_3\/q \LINS:UART:BUART:rx_state_2\/main_3 3.485
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(1,0) 1 \LINS:UART:BUART:rx_state_3\ \LINS:UART:BUART:rx_state_3\/clock_0 \LINS:UART:BUART:rx_state_3\/q 1.250
Route 1 \LINS:UART:BUART:rx_state_3\ \LINS:UART:BUART:rx_state_3\/q \LINS:UART:BUART:rx_state_2\/main_3 2.235
macrocell14 U(1,0) 1 \LINS:UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\LINS:UART:BUART:rx_state_3\/q \LINS:UART:BUART:rx_state_3\/main_3 3.485
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(1,0) 1 \LINS:UART:BUART:rx_state_3\ \LINS:UART:BUART:rx_state_3\/clock_0 \LINS:UART:BUART:rx_state_3\/q 1.250
macrocell15 U(1,0) 1 \LINS:UART:BUART:rx_state_3\ \LINS:UART:BUART:rx_state_3\/q \LINS:UART:BUART:rx_state_3\/main_3 2.235
macrocell15 U(1,0) 1 \LINS:UART:BUART:rx_state_3\ HOLD 0.000
Clock Skew 0.000
\LINS:bLIN:inact_detect\/q \LINS:bLIN:inact_detect\/main_1 3.490
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell33 U(0,0) 1 \LINS:bLIN:inact_detect\ \LINS:bLIN:inact_detect\/clock_0 \LINS:bLIN:inact_detect\/q 1.250
macrocell33 U(0,0) 1 \LINS:bLIN:inact_detect\ \LINS:bLIN:inact_detect\/q \LINS:bLIN:inact_detect\/main_1 2.240
macrocell33 U(0,0) 1 \LINS:bLIN:inact_detect\ HOLD 0.000
Clock Skew 0.000
\LINS:UART:BUART:rx_state_2\/q \LINS:UART:BUART:rx_state_2\/main_4 3.491
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(1,0) 1 \LINS:UART:BUART:rx_state_2\ \LINS:UART:BUART:rx_state_2\/clock_0 \LINS:UART:BUART:rx_state_2\/q 1.250
macrocell14 U(1,0) 1 \LINS:UART:BUART:rx_state_2\ \LINS:UART:BUART:rx_state_2\/q \LINS:UART:BUART:rx_state_2\/main_4 2.241
macrocell14 U(1,0) 1 \LINS:UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\LINS:UART:BUART:rx_state_2\/q \LINS:UART:BUART:rx_state_3\/main_4 3.491
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(1,0) 1 \LINS:UART:BUART:rx_state_2\ \LINS:UART:BUART:rx_state_2\/clock_0 \LINS:UART:BUART:rx_state_2\/q 1.250
Route 1 \LINS:UART:BUART:rx_state_2\ \LINS:UART:BUART:rx_state_2\/q \LINS:UART:BUART:rx_state_3\/main_4 2.241
macrocell15 U(1,0) 1 \LINS:UART:BUART:rx_state_3\ HOLD 0.000
Clock Skew 0.000
\LINS:bLIN:state_2\/q \LINS:bLIN:break_flag\/main_2 3.539
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell41 U(0,3) 1 \LINS:bLIN:state_2\ \LINS:bLIN:state_2\/clock_0 \LINS:bLIN:state_2\/q 1.250
Route 1 \LINS:bLIN:state_2\ \LINS:bLIN:state_2\/q \LINS:bLIN:break_flag\/main_2 2.289
macrocell28 U(0,3) 1 \LINS:bLIN:break_flag\ HOLD 0.000
Clock Skew 0.000
\LINS:bLIN:state_2\/q \LINS:bLIN:state_2\/main_3 3.539
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell41 U(0,3) 1 \LINS:bLIN:state_2\ \LINS:bLIN:state_2\/clock_0 \LINS:bLIN:state_2\/q 1.250
macrocell41 U(0,3) 1 \LINS:bLIN:state_2\ \LINS:bLIN:state_2\/q \LINS:bLIN:state_2\/main_3 2.289
macrocell41 U(0,3) 1 \LINS:bLIN:state_2\ HOLD 0.000
Clock Skew 0.000
\LINS:bLIN:break_flag\/q \LINS:bLIN:break_flag\/main_0 3.550
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(0,3) 1 \LINS:bLIN:break_flag\ \LINS:bLIN:break_flag\/clock_0 \LINS:bLIN:break_flag\/q 1.250
macrocell28 U(0,3) 1 \LINS:bLIN:break_flag\ \LINS:bLIN:break_flag\/q \LINS:bLIN:break_flag\/main_0 2.300
macrocell28 U(0,3) 1 \LINS:bLIN:break_flag\ HOLD 0.000
Clock Skew 0.000
\LINS:bLIN:break_flag\/q \LINS:bLIN:state_2\/main_0 3.550
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(0,3) 1 \LINS:bLIN:break_flag\ \LINS:bLIN:break_flag\/clock_0 \LINS:bLIN:break_flag\/q 1.250
Route 1 \LINS:bLIN:break_flag\ \LINS:bLIN:break_flag\/q \LINS:bLIN:state_2\/main_0 2.300
macrocell41 U(0,3) 1 \LINS:bLIN:state_2\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ LINS_IntClk
Source Destination Delay (ns)
Net_40/q L_TXD_1(0)_PAD 23.297
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(0,1) 1 Net_40 Net_40/clock_0 Net_40/q 1.250
Route 1 Net_40 Net_40/q L_TXD_1(0)/pin_input 5.847
iocell P5[6] 1 L_TXD_1(0) L_TXD_1(0)/pin_input L_TXD_1(0)/pad_out 16.200
Route 1 L_TXD_1(0)_PAD L_TXD_1(0)/pad_out L_TXD_1(0)_PAD 0.000
Clock Clock path delay 0.000