Static Timing Analysis

Project : secondslave_creator22
Build Time : 10/31/13 14:05:30
Device : CY8C5868AXI-LP035
Temperature : -40C - 85/125C
Vdda : 5.00
Vddd : 5.00
Vio0 : 5.00
Vio1 : 5.00
Vio2 : 5.00
Vio3 : 5.00
Voltage : 5.0
Vusb : 5.00
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
LINS_IntClk CyMASTER_CLK 307.692 kHz 307.692 kHz 49.020 MHz
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 63.500 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
L_RXD_1(0)/fb \LINS:bLIN:StsReg\/status_1 63.500 MHz 15.748 25.919
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[7] 1 L_RXD_1(0) L_RXD_1(0)/in_clock L_RXD_1(0)/fb 1.948
Route 1 Net_1 L_RXD_1(0)/fb \LINS:bLIN:edge_detect\/main_0 6.581
macrocell30 U(3,2) 1 \LINS:bLIN:edge_detect\ \LINS:bLIN:edge_detect\/main_0 \LINS:bLIN:edge_detect\/q 3.350
Route 1 \LINS:bLIN:edge_detect\ \LINS:bLIN:edge_detect\/q \LINS:bLIN:StsReg\/status_1 2.299
statusicell3 U(3,2) 1 \LINS:bLIN:StsReg\ SETUP 1.570
Clock Skew 0.000
L_RXD_1(0)/fb \LINS:bLIN:state_1\/main_3 77.202 MHz 12.953 28.714
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[7] 1 L_RXD_1(0) L_RXD_1(0)/in_clock L_RXD_1(0)/fb 1.948
Route 1 Net_1 L_RXD_1(0)/fb \LINS:bLIN:state_1\/main_3 7.495
macrocell40 U(3,3) 1 \LINS:bLIN:state_1\ SETUP 3.510
Clock Skew 0.000
L_RXD_1(0)/fb \LINS:Net_630\/main_1 88.865 MHz 11.253 30.414
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[7] 1 L_RXD_1(0) L_RXD_1(0)/in_clock L_RXD_1(0)/fb 1.948
Route 1 Net_1 L_RXD_1(0)/fb \LINS:Net_630\/main_1 5.795
macrocell3 U(3,1) 1 \LINS:Net_630\ SETUP 3.510
Clock Skew 0.000
L_RXD_1(0)/fb \LINS:bLIN:state_2\/main_3 88.865 MHz 11.253 30.414
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[7] 1 L_RXD_1(0) L_RXD_1(0)/in_clock L_RXD_1(0)/fb 1.948
Route 1 Net_1 L_RXD_1(0)/fb \LINS:bLIN:state_2\/main_3 5.795
macrocell41 U(3,1) 1 \LINS:bLIN:state_2\ SETUP 3.510
Clock Skew 0.000
L_RXD_1(0)/fb \LINS:bLIN:state_0\/main_3 89.896 MHz 11.124 30.543
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[7] 1 L_RXD_1(0) L_RXD_1(0)/in_clock L_RXD_1(0)/fb 1.948
Route 1 Net_1 L_RXD_1(0)/fb \LINS:bLIN:state_0\/main_3 5.666
macrocell39 U(3,1) 1 \LINS:bLIN:state_0\ SETUP 3.510
Clock Skew 0.000
L_RXD_1(0)/fb \LINS:bLIN:inact_state_0\/main_1 96.126 MHz 10.403 31.264
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[7] 1 L_RXD_1(0) L_RXD_1(0)/in_clock L_RXD_1(0)/fb 1.948
Route 1 Net_1 L_RXD_1(0)/fb \LINS:bLIN:inact_state_0\/main_1 4.945
macrocell34 U(3,0) 1 \LINS:bLIN:inact_state_0\ SETUP 3.510
Clock Skew 0.000
L_RXD_1(0)/fb \LINS:bLIN:inact_state_1\/main_1 96.126 MHz 10.403 31.264
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[7] 1 L_RXD_1(0) L_RXD_1(0)/in_clock L_RXD_1(0)/fb 1.948
Route 1 Net_1 L_RXD_1(0)/fb \LINS:bLIN:inact_state_1\/main_1 4.945
macrocell35 U(3,0) 1 \LINS:bLIN:inact_state_1\ SETUP 3.510
Clock Skew 0.000
L_RXD_1(0)/fb \LINS:bLIN:inact_state_2\/main_1 96.126 MHz 10.403 31.264
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[7] 1 L_RXD_1(0) L_RXD_1(0)/in_clock L_RXD_1(0)/fb 1.948
Route 1 Net_1 L_RXD_1(0)/fb \LINS:bLIN:inact_state_2\/main_1 4.945
macrocell36 U(3,0) 1 \LINS:bLIN:inact_state_2\ SETUP 3.510
Clock Skew 0.000
L_RXD_1(0)/fb \LINS:bLIN:rxd_reg\/main_0 96.126 MHz 10.403 31.264
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[7] 1 L_RXD_1(0) L_RXD_1(0)/in_clock L_RXD_1(0)/fb 1.948
Route 1 Net_1 L_RXD_1(0)/fb \LINS:bLIN:rxd_reg\/main_0 4.945
macrocell38 U(3,0) 1 \LINS:bLIN:rxd_reg\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 3250ns(307.692 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\LINS:bLIN:state_2\/q \LINS:bLIN:LINDp:u0\/cs_addr_2 49.020 MHz 20.400 3229.600
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell41 U(3,1) 1 \LINS:bLIN:state_2\ \LINS:bLIN:state_2\/clock_0 \LINS:bLIN:state_2\/q 1.250
Route 1 \LINS:bLIN:state_2\ \LINS:bLIN:state_2\/q \LINS:bLIN:LINDp:u0\/cs_addr_2 7.620
datapathcell4 U(3,3) 1 \LINS:bLIN:LINDp:u0\ SETUP 11.530
Clock Skew 0.000
\LINS:UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \LINS:UART:BUART:sTX:TxSts\/status_0 53.079 MHz 18.840 3231.160
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,3) 1 \LINS:UART:BUART:sTX:TxShifter:u0\ \LINS:UART:BUART:sTX:TxShifter:u0\/clock \LINS:UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \LINS:UART:BUART:tx_fifo_empty\ \LINS:UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \LINS:UART:BUART:tx_status_0\/main_2 5.709
macrocell25 U(2,2) 1 \LINS:UART:BUART:tx_status_0\ \LINS:UART:BUART:tx_status_0\/main_2 \LINS:UART:BUART:tx_status_0\/q 3.350
Route 1 \LINS:UART:BUART:tx_status_0\ \LINS:UART:BUART:tx_status_0\/q \LINS:UART:BUART:sTX:TxSts\/status_0 2.931
statusicell2 U(2,3) 1 \LINS:UART:BUART:sTX:TxSts\ SETUP 1.570
Clock Skew 0.000
\LINS:bLIN:state_0\/q \LINS:bLIN:LINDp:u0\/cs_addr_0 56.449 MHz 17.715 3232.285
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell39 U(3,1) 1 \LINS:bLIN:state_0\ \LINS:bLIN:state_0\/clock_0 \LINS:bLIN:state_0\/q 1.250
Route 1 \LINS:bLIN:state_0\ \LINS:bLIN:state_0\/q \LINS:bLIN:LINDp:u0\/cs_addr_0 4.935
datapathcell4 U(3,3) 1 \LINS:bLIN:LINDp:u0\ SETUP 11.530
Clock Skew 0.000
\LINS:UART:BUART:sTX:sCLOCK:TxBitCounter\/count_2 \LINS:UART:BUART:sTX:TxShifter:u0\/cs_addr_0 57.274 MHz 17.460 3232.540
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,2) 1 \LINS:UART:BUART:sTX:sCLOCK:TxBitCounter\ \LINS:UART:BUART:sTX:sCLOCK:TxBitCounter\/clock \LINS:UART:BUART:sTX:sCLOCK:TxBitCounter\/count_2 2.110
Route 1 \LINS:UART:BUART:txbitcount_2\ \LINS:UART:BUART:sTX:sCLOCK:TxBitCounter\/count_2 \LINS:UART:BUART:tx_bitclk_enable_pre\/main_0 2.797
macrocell21 U(2,2) 1 \LINS:UART:BUART:tx_bitclk_enable_pre\ \LINS:UART:BUART:tx_bitclk_enable_pre\/main_0 \LINS:UART:BUART:tx_bitclk_enable_pre\/q 3.350
Route 1 \LINS:UART:BUART:tx_bitclk_enable_pre\ \LINS:UART:BUART:tx_bitclk_enable_pre\/q \LINS:UART:BUART:sTX:TxShifter:u0\/cs_addr_0 2.913
datapathcell2 U(2,3) 1 \LINS:UART:BUART:sTX:TxShifter:u0\ SETUP 6.290
Clock Skew 0.000
\LINS:UART:BUART:sTX:sCLOCK:TxBitCounter\/count_1 \LINS:UART:BUART:sTX:TxShifter:u0\/cs_addr_0 57.293 MHz 17.454 3232.546
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,2) 1 \LINS:UART:BUART:sTX:sCLOCK:TxBitCounter\ \LINS:UART:BUART:sTX:sCLOCK:TxBitCounter\/clock \LINS:UART:BUART:sTX:sCLOCK:TxBitCounter\/count_1 2.110
Route 1 \LINS:UART:BUART:txbitcount_1\ \LINS:UART:BUART:sTX:sCLOCK:TxBitCounter\/count_1 \LINS:UART:BUART:tx_bitclk_enable_pre\/main_1 2.791
macrocell21 U(2,2) 1 \LINS:UART:BUART:tx_bitclk_enable_pre\ \LINS:UART:BUART:tx_bitclk_enable_pre\/main_1 \LINS:UART:BUART:tx_bitclk_enable_pre\/q 3.350
Route 1 \LINS:UART:BUART:tx_bitclk_enable_pre\ \LINS:UART:BUART:tx_bitclk_enable_pre\/q \LINS:UART:BUART:sTX:TxShifter:u0\/cs_addr_0 2.913
datapathcell2 U(2,3) 1 \LINS:UART:BUART:sTX:TxShifter:u0\ SETUP 6.290
Clock Skew 0.000
\LINS:UART:BUART:sTX:sCLOCK:TxBitCounter\/count_0 \LINS:UART:BUART:sTX:TxShifter:u0\/cs_addr_0 57.300 MHz 17.452 3232.548
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,2) 1 \LINS:UART:BUART:sTX:sCLOCK:TxBitCounter\ \LINS:UART:BUART:sTX:sCLOCK:TxBitCounter\/clock \LINS:UART:BUART:sTX:sCLOCK:TxBitCounter\/count_0 2.110
Route 1 \LINS:UART:BUART:txbitcount_0\ \LINS:UART:BUART:sTX:sCLOCK:TxBitCounter\/count_0 \LINS:UART:BUART:tx_bitclk_enable_pre\/main_2 2.789
macrocell21 U(2,2) 1 \LINS:UART:BUART:tx_bitclk_enable_pre\ \LINS:UART:BUART:tx_bitclk_enable_pre\/main_2 \LINS:UART:BUART:tx_bitclk_enable_pre\/q 3.350
Route 1 \LINS:UART:BUART:tx_bitclk_enable_pre\ \LINS:UART:BUART:tx_bitclk_enable_pre\/q \LINS:UART:BUART:sTX:TxShifter:u0\/cs_addr_0 2.913
datapathcell2 U(2,3) 1 \LINS:UART:BUART:sTX:TxShifter:u0\ SETUP 6.290
Clock Skew 0.000
\LINS:bLIN:inact_state_1\/q \LINS:bLIN:InactFSM:BusInactDp:u0\/cs_addr_1 57.707 MHz 17.329 3232.671
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell35 U(3,0) 1 \LINS:bLIN:inact_state_1\ \LINS:bLIN:inact_state_1\/clock_0 \LINS:bLIN:inact_state_1\/q 1.250
Route 1 \LINS:bLIN:inact_state_1\ \LINS:bLIN:inact_state_1\/q \LINS:bLIN:InactFSM:BusInactDp:u0\/cs_addr_1 4.549
datapathcell3 U(3,0) 1 \LINS:bLIN:InactFSM:BusInactDp:u0\ SETUP 11.530
Clock Skew 0.000
\LINS:UART:BUART:pollcount_1\/q \LINS:UART:BUART:sRX:RxShifter:u0\/route_si 58.211 MHz 17.179 3232.821
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(2,1) 1 \LINS:UART:BUART:pollcount_1\ \LINS:UART:BUART:pollcount_1\/clock_0 \LINS:UART:BUART:pollcount_1\/q 1.250
Route 1 \LINS:UART:BUART:pollcount_1\ \LINS:UART:BUART:pollcount_1\/q \LINS:UART:BUART:rx_postpoll\/main_0 4.493
macrocell12 U(2,1) 1 \LINS:UART:BUART:rx_postpoll\ \LINS:UART:BUART:rx_postpoll\/main_0 \LINS:UART:BUART:rx_postpoll\/q 3.350
Route 1 \LINS:UART:BUART:rx_postpoll\ \LINS:UART:BUART:rx_postpoll\/q \LINS:UART:BUART:sRX:RxShifter:u0\/route_si 2.876
datapathcell1 U(2,0) 1 \LINS:UART:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
\LINS:UART:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \LINS:UART:BUART:sRX:RxSts\/status_4 59.602 MHz 16.778 3233.222
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,0) 1 \LINS:UART:BUART:sRX:RxShifter:u0\ \LINS:UART:BUART:sRX:RxShifter:u0\/clock \LINS:UART:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \LINS:UART:BUART:rx_fifofull\ \LINS:UART:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \LINS:UART:BUART:rx_status_4\/main_1 2.244
macrocell18 U(3,0) 1 \LINS:UART:BUART:rx_status_4\ \LINS:UART:BUART:rx_status_4\/main_1 \LINS:UART:BUART:rx_status_4\/q 3.350
Route 1 \LINS:UART:BUART:rx_status_4\ \LINS:UART:BUART:rx_status_4\/q \LINS:UART:BUART:sRX:RxSts\/status_4 4.334
statusicell1 U(3,1) 1 \LINS:UART:BUART:sRX:RxSts\ SETUP 1.570
Clock Skew 0.000
\LINS:bLIN:state_2\/q \LINS:bLIN:LINDp:u0\/f0_load 60.720 MHz 16.469 3233.531
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell41 U(3,1) 1 \LINS:bLIN:state_2\ \LINS:bLIN:state_2\/clock_0 \LINS:bLIN:state_2\/q 1.250
Route 1 \LINS:bLIN:state_2\ \LINS:bLIN:state_2\/q \LINS:bLIN:f0_load\/main_0 7.614
macrocell31 U(3,3) 1 \LINS:bLIN:f0_load\ \LINS:bLIN:f0_load\/main_0 \LINS:bLIN:f0_load\/q 3.350
Route 1 \LINS:bLIN:f0_load\ \LINS:bLIN:f0_load\/q \LINS:bLIN:LINDp:u0\/f0_load 2.325
datapathcell4 U(3,3) 1 \LINS:bLIN:LINDp:u0\ SETUP 1.930
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
L_RXD_1(0)/fb \LINS:bLIN:inact_state_0\/main_1 6.893
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[7] 1 L_RXD_1(0) L_RXD_1(0)/in_clock L_RXD_1(0)/fb 1.948
Route 1 Net_1 L_RXD_1(0)/fb \LINS:bLIN:inact_state_0\/main_1 4.945
macrocell34 U(3,0) 1 \LINS:bLIN:inact_state_0\ HOLD 0.000
Clock Skew 0.000
L_RXD_1(0)/fb \LINS:bLIN:inact_state_1\/main_1 6.893
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[7] 1 L_RXD_1(0) L_RXD_1(0)/in_clock L_RXD_1(0)/fb 1.948
Route 1 Net_1 L_RXD_1(0)/fb \LINS:bLIN:inact_state_1\/main_1 4.945
macrocell35 U(3,0) 1 \LINS:bLIN:inact_state_1\ HOLD 0.000
Clock Skew 0.000
L_RXD_1(0)/fb \LINS:bLIN:inact_state_2\/main_1 6.893
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[7] 1 L_RXD_1(0) L_RXD_1(0)/in_clock L_RXD_1(0)/fb 1.948
Route 1 Net_1 L_RXD_1(0)/fb \LINS:bLIN:inact_state_2\/main_1 4.945
macrocell36 U(3,0) 1 \LINS:bLIN:inact_state_2\ HOLD 0.000
Clock Skew 0.000
L_RXD_1(0)/fb \LINS:bLIN:rxd_reg\/main_0 6.893
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[7] 1 L_RXD_1(0) L_RXD_1(0)/in_clock L_RXD_1(0)/fb 1.948
Route 1 Net_1 L_RXD_1(0)/fb \LINS:bLIN:rxd_reg\/main_0 4.945
macrocell38 U(3,0) 1 \LINS:bLIN:rxd_reg\ HOLD 0.000
Clock Skew 0.000
L_RXD_1(0)/fb \LINS:bLIN:state_0\/main_3 7.614
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[7] 1 L_RXD_1(0) L_RXD_1(0)/in_clock L_RXD_1(0)/fb 1.948
Route 1 Net_1 L_RXD_1(0)/fb \LINS:bLIN:state_0\/main_3 5.666
macrocell39 U(3,1) 1 \LINS:bLIN:state_0\ HOLD 0.000
Clock Skew 0.000
L_RXD_1(0)/fb \LINS:Net_630\/main_1 7.743
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[7] 1 L_RXD_1(0) L_RXD_1(0)/in_clock L_RXD_1(0)/fb 1.948
Route 1 Net_1 L_RXD_1(0)/fb \LINS:Net_630\/main_1 5.795
macrocell3 U(3,1) 1 \LINS:Net_630\ HOLD 0.000
Clock Skew 0.000
L_RXD_1(0)/fb \LINS:bLIN:state_2\/main_3 7.743
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[7] 1 L_RXD_1(0) L_RXD_1(0)/in_clock L_RXD_1(0)/fb 1.948
Route 1 Net_1 L_RXD_1(0)/fb \LINS:bLIN:state_2\/main_3 5.795
macrocell41 U(3,1) 1 \LINS:bLIN:state_2\ HOLD 0.000
Clock Skew 0.000
L_RXD_1(0)/fb \LINS:bLIN:state_1\/main_3 9.443
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[7] 1 L_RXD_1(0) L_RXD_1(0)/in_clock L_RXD_1(0)/fb 1.948
Route 1 Net_1 L_RXD_1(0)/fb \LINS:bLIN:state_1\/main_3 7.495
macrocell40 U(3,3) 1 \LINS:bLIN:state_1\ HOLD 0.000
Clock Skew 0.000
L_RXD_1(0)/fb \LINS:bLIN:StsReg\/status_1 12.178
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P3[7] 1 L_RXD_1(0) L_RXD_1(0)/in_clock L_RXD_1(0)/fb 1.948
Route 1 Net_1 L_RXD_1(0)/fb \LINS:bLIN:edge_detect\/main_0 6.581
macrocell30 U(3,2) 1 \LINS:bLIN:edge_detect\ \LINS:bLIN:edge_detect\/main_0 \LINS:bLIN:edge_detect\/q 3.350
Route 1 \LINS:bLIN:edge_detect\ \LINS:bLIN:edge_detect\/q \LINS:bLIN:StsReg\/status_1 2.299
statusicell3 U(3,2) 1 \LINS:bLIN:StsReg\ HOLD -2.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\LINS:UART:BUART:rx_status_3\/q \LINS:UART:BUART:sRX:RxSts\/status_3 2.124
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(2,0) 1 \LINS:UART:BUART:rx_status_3\ \LINS:UART:BUART:rx_status_3\/clock_0 \LINS:UART:BUART:rx_status_3\/q 1.250
Route 1 \LINS:UART:BUART:rx_status_3\ \LINS:UART:BUART:rx_status_3\/q \LINS:UART:BUART:sRX:RxSts\/status_3 2.874
statusicell1 U(3,1) 1 \LINS:UART:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\LINS:bLIN:break_flag\/q \LINS:bLIN:break_flag\/main_0 3.553
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell28 U(3,2) 1 \LINS:bLIN:break_flag\ \LINS:bLIN:break_flag\/clock_0 \LINS:bLIN:break_flag\/q 1.250
macrocell28 U(3,2) 1 \LINS:bLIN:break_flag\ \LINS:bLIN:break_flag\/q \LINS:bLIN:break_flag\/main_0 2.303
macrocell28 U(3,2) 1 \LINS:bLIN:break_flag\ HOLD 0.000
Clock Skew 0.000
\LINS:bLIN:inact_detect\/q \LINS:bLIN:inact_detect\/main_1 3.556
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell33 U(3,1) 1 \LINS:bLIN:inact_detect\ \LINS:bLIN:inact_detect\/clock_0 \LINS:bLIN:inact_detect\/q 1.250
macrocell33 U(3,1) 1 \LINS:bLIN:inact_detect\ \LINS:bLIN:inact_detect\/q \LINS:bLIN:inact_detect\/main_1 2.306
macrocell33 U(3,1) 1 \LINS:bLIN:inact_detect\ HOLD 0.000
Clock Skew 0.000
\LINS:bLIN:rxd_mux_ctrl\/q \LINS:Net_630\/main_0 3.571
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell37 U(3,1) 1 \LINS:bLIN:rxd_mux_ctrl\ \LINS:bLIN:rxd_mux_ctrl\/clock_0 \LINS:bLIN:rxd_mux_ctrl\/q 1.250
Route 1 \LINS:bLIN:rxd_mux_ctrl\ \LINS:bLIN:rxd_mux_ctrl\/q \LINS:Net_630\/main_0 2.321
macrocell3 U(3,1) 1 \LINS:Net_630\ HOLD 0.000
Clock Skew 0.000
\LINS:bLIN:rxd_mux_ctrl\/q \LINS:bLIN:rxd_mux_ctrl\/main_2 3.571
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell37 U(3,1) 1 \LINS:bLIN:rxd_mux_ctrl\ \LINS:bLIN:rxd_mux_ctrl\/clock_0 \LINS:bLIN:rxd_mux_ctrl\/q 1.250
macrocell37 U(3,1) 1 \LINS:bLIN:rxd_mux_ctrl\ \LINS:bLIN:rxd_mux_ctrl\/q \LINS:bLIN:rxd_mux_ctrl\/main_2 2.321
macrocell37 U(3,1) 1 \LINS:bLIN:rxd_mux_ctrl\ HOLD 0.000
Clock Skew 0.000
\LINS:Net_622\/q \LINS:UART:BUART:sTX:TxShifter:u0\/clk_en 3.572
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(3,3) 1 \LINS:Net_622\ \LINS:Net_622\/clock_0 \LINS:Net_622\/q 1.250
Route 1 \LINS:Net_622\ \LINS:Net_622\/q \LINS:UART:BUART:sTX:TxShifter:u0\/clk_en 2.322
datapathcell2 U(2,3) 1 \LINS:UART:BUART:sTX:TxShifter:u0\ HOLD 0.000
Clock Skew 0.000
\LINS:Net_622\/q \LINS:UART:BUART:sTX:TxSts\/clk_en 3.572
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(3,3) 1 \LINS:Net_622\ \LINS:Net_622\/clock_0 \LINS:Net_622\/q 1.250
Route 1 \LINS:Net_622\ \LINS:Net_622\/q \LINS:UART:BUART:sTX:TxSts\/clk_en 2.322
statusicell2 U(2,3) 1 \LINS:UART:BUART:sTX:TxSts\ HOLD 0.000
Clock Skew 0.000
\LINS:Net_622\/q \LINS:UART:BUART:tx_state_0\/clk_en 3.572
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(3,3) 1 \LINS:Net_622\ \LINS:Net_622\/clock_0 \LINS:Net_622\/q 1.250
Route 1 \LINS:Net_622\ \LINS:Net_622\/q \LINS:UART:BUART:tx_state_0\/clk_en 2.322
macrocell22 U(2,3) 1 \LINS:UART:BUART:tx_state_0\ HOLD 0.000
Clock Skew 0.000
\LINS:Net_622\/q \LINS:UART:BUART:tx_state_1\/clk_en 3.572
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(3,3) 1 \LINS:Net_622\ \LINS:Net_622\/clock_0 \LINS:Net_622\/q 1.250
Route 1 \LINS:Net_622\ \LINS:Net_622\/q \LINS:UART:BUART:tx_state_1\/clk_en 2.322
macrocell23 U(2,3) 1 \LINS:UART:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
\LINS:Net_622\/q \LINS:UART:BUART:tx_state_2\/clk_en 3.572
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(3,3) 1 \LINS:Net_622\ \LINS:Net_622\/clock_0 \LINS:Net_622\/q 1.250
Route 1 \LINS:Net_622\ \LINS:Net_622\/q \LINS:UART:BUART:tx_state_2\/clk_en 2.322
macrocell24 U(2,3) 1 \LINS:UART:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ LINS_IntClk
Source Destination Delay (ns)
Net_2/q L_TXD_1(0)_PAD 23.024
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(3,2) 1 Net_2 Net_2/clock_0 Net_2/q 1.250
Route 1 Net_2 Net_2/q L_TXD_1(0)/pin_input 6.436
iocell2 P3[5] 1 L_TXD_1(0) L_TXD_1(0)/pin_input L_TXD_1(0)/pad_out 15.338
Route 1 L_TXD_1(0)_PAD L_TXD_1(0)/pad_out L_TXD_1(0)_PAD 0.000
Clock Clock path delay 0.000