library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity SerialMultiplier is port( clock : in std_ulogic; newData : in std_ulogic; multiplicand : in signed; multiplicator : in signed; product : out unsigned; done : out std_ulogic ); end; architecture processStructure of SerialMultiplier is signal multiplicandReg : unsigned(multiplicand'range) := (others => '0'); signal multiplicatorShiftReg : unsigned(multiplicator'range) := (others => '0'); signal highProductReg : unsigned(multiplicand'range) := (others => '0'); signal partialProduct : unsigned(multiplicand'range) := (others => '0'); signal lowProductShiftReg : unsigned(multiplicator'range) := (others => '0'); signal processingShiftReg : unsigned(multiplicator'high + 2 downto 0) := (others => '0'); signal lastNewData : std_ulogic := '0'; signal set : std_ulogic := '0'; signal partialSum : unsigned(multiplicand'high + 1 downto 0) := (others => '0'); begin product <= unsigned(highProductReg & lowProductShiftReg); done <= processingShiftReg(0); partialproduct <= multiplicandReg when multiplicatorShiftReg(0) = '1' else (partialproduct'range => '0'); partialSum <= RESIZE(partialProduct, multiplicand'high + 2) + RESIZE(highProductReg, multiplicand'high + 2); p : process(clock) begin if rising_edge(clock) then if newData = '1' and not lastnewdata = '1' then set <= '1'; else set <= '0'; end if; if set = '1' then multiplicatorShiftReg <= unsigned(multiplicator); multiplicandReg <= unsigned(multiplicand); processingShiftReg(processingShiftReg'high) <= '1'; highProductReg <= (highProductReg'range => '0'); lowProductShiftReg <= (lowProductShiftReg'range => '0'); else --partialSum <= RESIZE(partialProduct, multiplicand'high + 2) + RESIZE(highProductReg, multiplicand'high + 2); highProductReg <= partialSum(partialSum'high downto 1); lowProductShiftReg(lowProductShiftReg'high) <= partialSum(0); lowProductShiftReg(lowProductShiftReg'high - 1 downto 0) <= lowProductShiftReg(lowProductShiftReg'left downto 1); multiplicatorShiftReg <= '0' & multiplicatorShiftReg(multiplicatorShiftReg'left downto 1); processingShiftReg <= '0' & processingShiftReg(processingShiftReg'left downto 1); end if; lastnewData <= newData; end if; end process; end;