#ifndef CYGONCE_PKGCONF_HAL_CORTEXM_STM32_H
#define CYGONCE_PKGCONF_HAL_CORTEXM_STM32_H
/*
 * File <pkgconf/hal_cortexm_stm32.h>
 *
 * This file is generated automatically by the configuration
 * system. It should not be edited. Any changes to this file
 * may be overwritten.
 */

#define CYGHWR_HAL_CORTEXM_STM32 F407VG
#define CYGHWR_HAL_CORTEXM_STM32_F407VG
#define CYGHWR_HAL_CORTEXM_STM32_FAMILY F4
#define CYGHWR_HAL_CORTEXM_STM32_FAMILY_F4
#define CYGHWR_HAL_CORTEXM_STM32_FAMILY_HIPERFORMANCE 1
#define CYGHWR_HAL_CORTEXM_STM32_F4 F407VG
#define CYGHWR_HAL_CORTEXM_STM32_F4_F407VG
#define CYGHWR_HAL_CORTEXM_STM32_CONNECTIVITY 1
#define CYGNUM_HAL_CORTEXM_PRIORITY_LEVEL_BITS 4
#define CYGNUM_HAL_CORTEXM_PRIORITY_LEVEL_BITS_4
#define CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_SOURCE HSE
#define CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_SOURCE_HSE
#define CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV 8
#define CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_PREDIV_8
#define CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL 336
#define CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_MUL_336
#define CYGHWR_HAL_CORTEXM_STM32_CLOCK_SYSCLK_DIV 2
#define CYGHWR_HAL_CORTEXM_STM32_CLOCK_SYSCLK_DIV_2
#define CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV 1
#define CYGHWR_HAL_CORTEXM_STM32_CLOCK_HCLK_DIV_1
#define CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK1_DIV 4
#define CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK1_DIV_4
#define CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK2_DIV 2
#define CYGHWR_HAL_CORTEXM_STM32_CLOCK_PCLK2_DIV_2
#define CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLLQ_DIV 7
#define CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLLQ_DIV_7
#define CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY 0x000000E0
#define CYGNUM_HAL_KERNEL_COUNTERS_CLOCK_ISR_DEFAULT_PRIORITY_0x000000E0
#define CYGNUM_HAL_RTC_NUMERATOR 1000000000
#define CYGNUM_HAL_RTC_NUMERATOR_1000000000
#define CYGNUM_HAL_RTC_DENOMINATOR 1000
#define CYGNUM_HAL_RTC_DENOMINATOR_1000
#define CYGNUM_HAL_RTC_PERIOD 1000
#define CYGNUM_HAL_RTC_PERIOD_1000
#define CYGINT_HAL_STM32_UART0 0
#define CYGINT_HAL_STM32_UART0_0
#define CYGINT_HAL_STM32_UART1 0
#define CYGINT_HAL_STM32_UART1_0
#define CYGINT_HAL_STM32_UART2 0
#define CYGINT_HAL_STM32_UART2_0
#define CYGINT_HAL_STM32_UART3 1
#define CYGINT_HAL_STM32_UART3_1
#define CYGINT_HAL_STM32_UART4 0
#define CYGINT_HAL_STM32_UART4_0
#define CYGINT_HAL_STM32_UART5 0
#define CYGINT_HAL_STM32_UART5_0
#define CYGHWR_HAL_STM32_UART2_REMAP NONE
#define CYGHWR_HAL_STM32_UART2_REMAP_NONE
#define CYGPKG_HAL_CORTEXM_STM32_OPTIONS 1

#endif
