 
cpldfit:  version I.31                              Xilinx Inc.
                                  Fitter Report
Design Name: versuch2                            Date:  2-10-2007, 12:27PM
Device Used: XC9572XL-5-PC44
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
21 /72  ( 29%) 2   /360  (  1%) 3  /216 (  1%)   0  /72  (  0%) 21 /34  ( 62%)

** Function Block Resources **

Function    Mcells      FB Inps     Pterms      IO          
Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot    
FB1           5/18        3/54        2/90       5/ 9
FB2           6/18        0/54        0/90       6/ 9
FB3           6/18        0/54        0/90       6/ 9
FB4           4/18        0/54        0/90       4/ 7
             -----       -----       -----      -----    
             21/72        3/216       2/360     21/34 

* - Resource is exhausted

** Global Control Resources **

Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    3           3    |  I/O              :    22      28
Output        :   21          21    |  GCK/IO           :     0       3
Bidirectional :    0           0    |  GTS/IO           :     1       2
GCK           :    0           0    |  GSR/IO           :     1       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     24          24

** Power Data **

There are 21 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
*************************  Summary of Mapped Logic  ************************

** 21 Outputs **

Signal              Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                Pts   Inps          No.  Type    Use     Mode Rate State
a<16>               0     0     FB1_2   1    I/O     O       STD  FAST 
a<2>                0     0     FB1_6   3    I/O     O       STD  FAST 
oe                  1     2     FB1_8   4    I/O     O       STD  FAST 
we                  1     2     FB1_15  8    I/O     O       STD  FAST 
a<9>                0     0     FB1_17  9    I/O     O       STD  FAST 
a<7>                0     0     FB2_2   35   I/O     O       STD  FAST 
a<14>               0     0     FB2_5   36   I/O     O       STD  FAST 
a<11>               0     0     FB2_6   37   I/O     O       STD  FAST 
a<6>                0     0     FB2_8   38   I/O     O       STD  FAST 
a<3>                0     0     FB2_15  43   I/O     O       STD  FAST 
a<17>               0     0     FB2_17  44   I/O     O       STD  FAST 
a<8>                0     0     FB3_2   11   I/O     O       STD  FAST 
a<18>               0     0     FB3_5   12   I/O     O       STD  FAST 
a<15>               0     0     FB3_8   13   I/O     O       STD  FAST 
a<12>               0     0     FB3_11  18   I/O     O       STD  FAST 
a<0>                0     0     FB3_15  20   I/O     O       STD  FAST 
a<4>                0     0     FB3_17  22   I/O     O       STD  FAST 
a<13>               0     0     FB4_5   26   I/O     O       STD  FAST 
a<10>               0     0     FB4_8   27   I/O     O       STD  FAST 
a<5>                0     0     FB4_14  29   I/O     O       STD  FAST 
a<1>                0     0     FB4_17  34   I/O     O       STD  FAST 

** 3 Inputs **

Signal              Loc     Pin  Pin     Pin     
Name                        No.  Type    Use     
c2                  FB2_9   39   GSR/I/O I
sel                 FB2_11  40   GTS/I/O I
c1                  FB4_15  33   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X            - Signal used as input to the macrocell logic.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               3/51
Number of signals used by logic mapping into function block:  3
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB1_1         (b)     
a<16>                 0       0     0   5     FB1_2   1     I/O     O
(unused)              0       0     0   5     FB1_3         (b)     
(unused)              0       0     0   5     FB1_4         (b)     
(unused)              0       0     0   5     FB1_5   2     I/O     
a<2>                  0       0     0   5     FB1_6   3     I/O     O
(unused)              0       0     0   5     FB1_7         (b)     
oe                    1       0     0   4     FB1_8   4     I/O     O
(unused)              0       0     0   5     FB1_9   5     GCK/I/O 
(unused)              0       0     0   5     FB1_10        (b)     
(unused)              0       0     0   5     FB1_11  6     GCK/I/O 
(unused)              0       0     0   5     FB1_12        (b)     
(unused)              0       0     0   5     FB1_13        (b)     
(unused)              0       0     0   5     FB1_14  7     GCK/I/O 
we                    1       0     0   4     FB1_15  8     I/O     O
(unused)              0       0     0   5     FB1_16        (b)     
a<9>                  0       0     0   5     FB1_17  9     I/O     O
(unused)              0       0     0   5     FB1_18        (b)     

Signals Used by Logic in Function Block
  1: c1                 2: c2                 3: sel 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
a<16>                ........................................ 0
a<2>                 ........................................ 0
oe                   .XX..................................... 2
we                   X.X..................................... 2
a<9>                 ........................................ 0
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               0/54
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB2_1         (b)     
a<7>                  0       0     0   5     FB2_2   35    I/O     O
(unused)              0       0     0   5     FB2_3         (b)     
(unused)              0       0     0   5     FB2_4         (b)     
a<14>                 0       0     0   5     FB2_5   36    I/O     O
a<11>                 0       0     0   5     FB2_6   37    I/O     O
(unused)              0       0     0   5     FB2_7         (b)     
a<6>                  0       0     0   5     FB2_8   38    I/O     O
(unused)              0       0     0   5     FB2_9   39    GSR/I/O I
(unused)              0       0     0   5     FB2_10        (b)     
(unused)              0       0     0   5     FB2_11  40    GTS/I/O I
(unused)              0       0     0   5     FB2_12        (b)     
(unused)              0       0     0   5     FB2_13        (b)     
(unused)              0       0     0   5     FB2_14  42    GTS/I/O 
a<3>                  0       0     0   5     FB2_15  43    I/O     O
(unused)              0       0     0   5     FB2_16        (b)     
a<17>                 0       0     0   5     FB2_17  44    I/O     O
(unused)              0       0     0   5     FB2_18        (b)     

Signals Used by Logic in Function Block

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
a<7>                 ........................................ 0
a<14>                ........................................ 0
a<11>                ........................................ 0
a<6>                 ........................................ 0
a<3>                 ........................................ 0
a<17>                ........................................ 0
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               0/54
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB3_1         (b)     
a<8>                  0       0     0   5     FB3_2   11    I/O     O
(unused)              0       0     0   5     FB3_3         (b)     
(unused)              0       0     0   5     FB3_4         (b)     
a<18>                 0       0     0   5     FB3_5   12    I/O     O
(unused)              0       0     0   5     FB3_6         (b)     
(unused)              0       0     0   5     FB3_7         (b)     
a<15>                 0       0     0   5     FB3_8   13    I/O     O
(unused)              0       0     0   5     FB3_9   14    I/O     
(unused)              0       0     0   5     FB3_10        (b)     
a<12>                 0       0     0   5     FB3_11  18    I/O     O
(unused)              0       0     0   5     FB3_12        (b)     
(unused)              0       0     0   5     FB3_13        (b)     
(unused)              0       0     0   5     FB3_14  19    I/O     
a<0>                  0       0     0   5     FB3_15  20    I/O     O
(unused)              0       0     0   5     FB3_16  24    I/O     
a<4>                  0       0     0   5     FB3_17  22    I/O     O
(unused)              0       0     0   5     FB3_18        (b)     

Signals Used by Logic in Function Block

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
a<8>                 ........................................ 0
a<18>                ........................................ 0
a<15>                ........................................ 0
a<12>                ........................................ 0
a<0>                 ........................................ 0
a<4>                 ........................................ 0
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               0/54
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB4_1         (b)     
(unused)              0       0     0   5     FB4_2   25    I/O     
(unused)              0       0     0   5     FB4_3         (b)     
(unused)              0       0     0   5     FB4_4         (b)     
a<13>                 0       0     0   5     FB4_5   26    I/O     O
(unused)              0       0     0   5     FB4_6         (b)     
(unused)              0       0     0   5     FB4_7         (b)     
a<10>                 0       0     0   5     FB4_8   27    I/O     O
(unused)              0       0     0   5     FB4_9         (b)     
(unused)              0       0     0   5     FB4_10        (b)     
(unused)              0       0     0   5     FB4_11  28    I/O     
(unused)              0       0     0   5     FB4_12        (b)     
(unused)              0       0     0   5     FB4_13        (b)     
a<5>                  0       0     0   5     FB4_14  29    I/O     O
(unused)              0       0     0   5     FB4_15  33    I/O     I
(unused)              0       0     0   5     FB4_16        (b)     
a<1>                  0       0     0   5     FB4_17  34    I/O     O
(unused)              0       0     0   5     FB4_18        (b)     

Signals Used by Logic in Function Block

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
a<13>                ........................................ 0
a<10>                ........................................ 0
a<5>                 ........................................ 0
a<1>                 ........................................ 0
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********


a(0) <= '0';


a(1) <= '0';


a(2) <= '0';


a(3) <= '0';


a(4) <= '0';


a(5) <= '0';


a(6) <= '0';


a(7) <= '0';


a(8) <= '0';


a(9) <= '0';


a(10) <= '0';


a(11) <= '0';


a(12) <= '0';


a(13) <= '0';


a(14) <= '0';


a(15) <= '0';


a(16) <= '0';


a(17) <= '0';


a(18) <= '0';


oe <= (c2 AND NOT sel);


we <= (sel AND c1);

Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC9572XL-5-PC44


   --------------------------------  
  /6  5  4  3  2  1  44 43 42 41 40 \
 | 7                             39 | 
 | 8                             38 | 
 | 9                             37 | 
 | 10                            36 | 
 | 11        XC9572XL-5-PC44     35 | 
 | 12                            34 | 
 | 13                            33 | 
 | 14                            32 | 
 | 15                            31 | 
 | 16                            30 | 
 | 17                            29 | 
 \ 18 19 20 21 22 23 24 25 26 27 28 /
   --------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 a<16>                            23 GND                           
  2 KPR                              24 KPR                           
  3 a<2>                             25 KPR                           
  4 oe                               26 a<13>                         
  5 KPR                              27 a<10>                         
  6 KPR                              28 KPR                           
  7 KPR                              29 a<5>                          
  8 we                               30 TDO                           
  9 a<9>                             31 GND                           
 10 GND                              32 VCC                           
 11 a<8>                             33 c1                            
 12 a<18>                            34 a<1>                          
 13 a<15>                            35 a<7>                          
 14 KPR                              36 a<14>                         
 15 TDI                              37 a<11>                         
 16 TMS                              38 a<6>                          
 17 TCK                              39 c2                            
 18 a<12>                            40 sel                           
 19 KPR                              41 VCC                           
 20 a<0>                             42 KPR                           
 21 VCC                              43 a<3>                          
 22 a<4>                             44 a<17>                         


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         KPR  = Unused I/O with weak keeper (leave unconnected)
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc9572xl-5-PC44
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : STD
Ground on Unused IOs                        : OFF
Set I/O Pin Termination                     : KEEPER
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Input Limit                                 : 54
Pterm Limit                                 : 25
