 
cpldfit:  version I.34                              Xilinx Inc.
                                  Fitter Report
Design Name: VhdlEndTest                         Date:  2-27-2007,  3:44PM
Device Used: XC9572-7-PC84
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
28 /72  ( 39%) 77  /360  ( 21%) 44 /144 ( 31%)   26 /72  ( 36%) 6  /69  (  9%)

** Function Block Resources **

Function    Mcells      FB Inps     Signals     Pterms      IO          
Block       Used/Tot    Used/Tot    Used        Used/Tot    Used/Tot    
FB1           0/18        0/36        0           0/90       0/18
FB2           0/18        0/36        0           0/90       0/17
FB3          13/18       29/36       30          55/90       1/17
FB4          15/18       15/36       15          22/90       1/17
             -----       -----                   -----       -----     
             28/72       44/144                  77/360      2/69 

* - Resource is exhausted

** Global Control Resources **

Signal 'clkLatch1' mapped onto global clock net GCK1.
Signal 'clkLatch2' mapped onto global clock net GCK2.
Signal 'clk' mapped onto global clock net GCK3.
Global output enable net(s) unused.
Signal 'rst' mapped onto global set/reset net GSR.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    8           8    |  I/O              :    10      63
Output        :    2           2    |  GCK/IO           :     3       3
Bidirectional :    0           0    |  GTS/IO           :     0       2
GCK           :    3           3    |  GSR/IO           :     1       1
GTS           :    0           0    |
GSR           :    1           1    |
                 ----        ----
        Total     14          14

** Power Data **

There are 28 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
*************************  Summary of Mapped Logic  ************************

** 2 Outputs **

Signal                                                  Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                                                    Pts   Inps          No.  Type    Use     Mode Rate State
EndV1                                                   8     7     FB3_3   31   I/O     O       STD  FAST RESET
EndV2                                                   8     7     FB4_3   51   I/O     O       STD  FAST RESET

** 26 Buried Nodes **

Signal                                                  Total Total Loc     Pwr  Reg Init
Name                                                    Pts   Inps          Mode State
Mcompar__cmp_gt0000_AGB32/Mcompar__cmp_gt0000_AGB32_D2  19    18    FB3_2   STD  
FahrZaehler<7>                                          1     7     FB3_5   STD  RESET
FahrZaehler<6>                                          1     6     FB3_7   STD  RESET
FahrZaehler<5>                                          1     5     FB3_8   STD  RESET
FahrZaehler<4>                                          1     4     FB3_9   STD  RESET
FahrZaehler<3>                                          1     3     FB3_10  STD  RESET
FahrZaehler<2>                                          1     2     FB3_11  STD  RESET
FahrZaehler<1>                                          1     1     FB3_12  STD  RESET
FahrZaehler<0>                                          0     0     FB3_13  STD  RESET
FahrSpeicher1<1>                                        1     1     FB3_14  STD  RESET
Mcompar__cmp_gt0001_AGB32/Mcompar__cmp_gt0001_AGB32_D2  19    18    FB3_16  STD  
FahrSpeicher1<0>                                        1     1     FB3_18  STD  RESET
FahrSpeicher2<7>                                        1     1     FB4_5   STD  RESET
FahrSpeicher2<6>                                        1     1     FB4_6   STD  RESET
FahrSpeicher2<5>                                        1     1     FB4_7   STD  RESET
FahrSpeicher2<4>                                        1     1     FB4_8   STD  RESET
FahrSpeicher2<3>                                        1     1     FB4_9   STD  RESET
FahrSpeicher2<2>                                        1     1     FB4_10  STD  RESET
FahrSpeicher2<1>                                        1     1     FB4_11  STD  RESET
FahrSpeicher2<0>                                        1     1     FB4_12  STD  RESET
FahrSpeicher1<7>                                        1     1     FB4_13  STD  RESET
FahrSpeicher1<6>                                        1     1     FB4_14  STD  RESET
FahrSpeicher1<5>                                        1     1     FB4_15  STD  RESET
FahrSpeicher1<4>                                        1     1     FB4_16  STD  RESET
FahrSpeicher1<3>                                        1     1     FB4_17  STD  RESET
FahrSpeicher1<2>                                        1     1     FB4_18  STD  RESET

** 12 Inputs **

Signal                                                  Loc     Pin  Pin     Pin     
Name                                                            No.  Type    Use     
DATA<4>                                                 FB1_8   5    I/O     I
clkLatch1                                               FB1_9   9~   GCK/I/O GCK
clkLatch2                                               FB1_11  10~  GCK/I/O GCK
clk                                                     FB1_14  12~  GCK/I/O GCK
DATA<3>                                                 FB2_5   70   I/O     I
DATA<1>                                                 FB2_8   72   I/O     I
rst                                                     FB2_9   74~  GSR/I/O GSR
DATA<6>                                                 FB2_15  83   I/O     I
DATA<7>                                                 FB3_2   17   I/O     I
DATA<2>                                                 FB3_15  37   I/O     I
DATA<0>                                                 FB4_2   44   I/O     I
DATA<5>                                                 FB4_11  53   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@)         - Signal used as input (wire-AND input) to the macrocell logic.
               The number of Signals Used may exceed the number of FB Inputs
               Used due to wire-ANDing in the switch matrix.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               0/36
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB1_1   4     I/O     
(unused)              0       0     0   5     FB1_2   1     I/O     
(unused)              0       0     0   5     FB1_3   6     I/O     
(unused)              0       0     0   5     FB1_4   7     I/O     
(unused)              0       0     0   5     FB1_5   2     I/O     
(unused)              0       0     0   5     FB1_6   3     I/O     
(unused)              0       0     0   5     FB1_7   11    I/O     
(unused)              0       0     0   5     FB1_8   5     I/O     I
(unused)              0       0     0   5     FB1_9   9     GCK/I/O GCK
(unused)              0       0     0   5     FB1_10  13    I/O     
(unused)              0       0     0   5     FB1_11  10    GCK/I/O GCK
(unused)              0       0     0   5     FB1_12  18    I/O     
(unused)              0       0     0   5     FB1_13  20    I/O     
(unused)              0       0     0   5     FB1_14  12    GCK/I/O GCK
(unused)              0       0     0   5     FB1_15  14    I/O     
(unused)              0       0     0   5     FB1_16  23    I/O     
(unused)              0       0     0   5     FB1_17  15    I/O     
(unused)              0       0     0   5     FB1_18  24    I/O     
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               0/36
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB2_1   63    I/O     
(unused)              0       0     0   5     FB2_2   69    I/O     
(unused)              0       0     0   5     FB2_3   67    I/O     
(unused)              0       0     0   5     FB2_4   68    I/O     
(unused)              0       0     0   5     FB2_5   70    I/O     I
(unused)              0       0     0   5     FB2_6   71    I/O     
(unused)              0       0     0   5     FB2_7   76    GTS/I/O 
(unused)              0       0     0   5     FB2_8   72    I/O     I
(unused)              0       0     0   5     FB2_9   74    GSR/I/O GSR
(unused)              0       0     0   5     FB2_10  75    I/O     
(unused)              0       0     0   5     FB2_11  77    GTS/I/O 
(unused)              0       0     0   5     FB2_12  79    I/O     
(unused)              0       0     0   5     FB2_13  80    I/O     
(unused)              0       0     0   5     FB2_14  81    I/O     
(unused)              0       0     0   5     FB2_15  83    I/O     I
(unused)              0       0     0   5     FB2_16  82    I/O     
(unused)              0       0     0   5     FB2_17  84    I/O     
(unused)              0       0     0   5     FB2_18        (b)     
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               29/7
Number of signals used by logic mapping into function block:  30
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   \/5   0     FB3_1   25    I/O     (b)
Mcompar__cmp_gt0000_AGB32/Mcompar__cmp_gt0000_AGB32_D2
                     19      14<-   0   0     FB3_2   17    I/O     I
EndV1                 8       8<- /\5   0     FB3_3   31    I/O     O
(unused)              0       0   /\5   0     FB3_4   32    I/O     (b)
FahrZaehler<7>        1       0   /\3   1     FB3_5   19    I/O     (b)
(unused)              0       0     0   5     FB3_6   34    I/O     
FahrZaehler<6>        1       0     0   4     FB3_7   35    I/O     (b)
FahrZaehler<5>        1       0     0   4     FB3_8   21    I/O     (b)
FahrZaehler<4>        1       0     0   4     FB3_9   26    I/O     (b)
FahrZaehler<3>        1       0     0   4     FB3_10  40    I/O     (b)
FahrZaehler<2>        1       0     0   4     FB3_11  33    I/O     (b)
FahrZaehler<1>        1       0     0   4     FB3_12  41    I/O     (b)
FahrZaehler<0>        0       0     0   5     FB3_13  43    I/O     (b)
FahrSpeicher1<1>      1       0   \/4   0     FB3_14  36    I/O     (b)
(unused)              0       0   \/5   0     FB3_15  37    I/O     I
Mcompar__cmp_gt0001_AGB32/Mcompar__cmp_gt0001_AGB32_D2
                     19      14<-   0   0     FB3_16  45    I/O     (b)
(unused)              0       0   /\5   0     FB3_17  39    I/O     (b)
FahrSpeicher1<0>      1       0   \/4   0     FB3_18        (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$$OpTx$FX_DC$3_INV$311  11: FahrSpeicher1<6>  21: FahrZaehler<0>.LFBK 
  2: $OpTx$$OpTx$FX_DC$4_INV$312  12: FahrSpeicher1<7>  22: FahrZaehler<1>.LFBK 
  3: DATA<0>                      13: FahrSpeicher2<0>  23: FahrZaehler<2>.LFBK 
  4: DATA<1>                      14: FahrSpeicher2<1>  24: FahrZaehler<3>.LFBK 
  5: FahrSpeicher1<0>.LFBK        15: FahrSpeicher2<2>  25: FahrZaehler<4> 
  6: FahrSpeicher1<1>.LFBK        16: FahrSpeicher2<3>  26: FahrZaehler<4>.LFBK 
  7: FahrSpeicher1<2>             17: FahrSpeicher2<4>  27: FahrZaehler<5>.LFBK 
  8: FahrSpeicher1<3>             18: FahrSpeicher2<5>  28: FahrZaehler<6>.LFBK 
  9: FahrSpeicher1<4>             19: FahrSpeicher2<6>  29: FahrZaehler<7>.LFBK 
 10: FahrSpeicher1<5>             20: FahrSpeicher2<7>  30: Mcompar__cmp_gt0000_AGB32/Mcompar__cmp_gt0000_AGB32_D2.LFBK 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
Mcompar__cmp_gt0000_AGB32/Mcompar__cmp_gt0000_AGB32_D2 
                     X...XXXX@XXX........XXXX@XXXX........... 18      16
EndV1                .........XXX..............XXXX.......... 7       7
FahrZaehler<7>       ....................XXXX.XXX............ 7       7
FahrZaehler<6>       ....................XXXX.XX............. 6       6
FahrZaehler<5>       ....................XXXX.X.............. 5       5
FahrZaehler<4>       ....................XXXX................ 4       4
FahrZaehler<3>       ....................XXX................. 3       3
FahrZaehler<2>       ....................XX.................. 2       2
FahrZaehler<1>       ....................X................... 1       1
FahrZaehler<0>       ........................................ 0       0
FahrSpeicher1<1>     ...X.................................... 1       1
Mcompar__cmp_gt0001_AGB32/Mcompar__cmp_gt0001_AGB32_D2 
                     .X..........XXXX@XXXXXXX@XXXX........... 18      16
FahrSpeicher1<0>     ..X..................................... 1       1
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               15/21
Number of signals used by logic mapping into function block:  15
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB4_1   46    I/O     
(unused)              0       0   \/2   3     FB4_2   44    I/O     I
EndV2                 8       3<-   0   0     FB4_3   51    I/O     O
(unused)              0       0   /\1   4     FB4_4   52    I/O     (b)
FahrSpeicher2<7>      1       0     0   4     FB4_5   47    I/O     (b)
FahrSpeicher2<6>      1       0     0   4     FB4_6   54    I/O     (b)
FahrSpeicher2<5>      1       0     0   4     FB4_7   55    I/O     (b)
FahrSpeicher2<4>      1       0     0   4     FB4_8   48    I/O     (b)
FahrSpeicher2<3>      1       0     0   4     FB4_9   50    I/O     (b)
FahrSpeicher2<2>      1       0     0   4     FB4_10  57    I/O     (b)
FahrSpeicher2<1>      1       0     0   4     FB4_11  53    I/O     I
FahrSpeicher2<0>      1       0     0   4     FB4_12  58    I/O     (b)
FahrSpeicher1<7>      1       0     0   4     FB4_13  61    I/O     (b)
FahrSpeicher1<6>      1       0     0   4     FB4_14  56    I/O     (b)
FahrSpeicher1<5>      1       0     0   4     FB4_15  65    I/O     (b)
FahrSpeicher1<4>      1       0     0   4     FB4_16  62    I/O     (b)
FahrSpeicher1<3>      1       0     0   4     FB4_17  66    I/O     (b)
FahrSpeicher1<2>      1       0     0   4     FB4_18        (b)     (b)

Signals Used by Logic in Function Block
  1: DATA<0>            6: DATA<5>                11: FahrSpeicher2<7>.LFBK 
  2: DATA<1>            7: DATA<6>                12: FahrZaehler<5> 
  3: DATA<2>            8: DATA<7>                13: FahrZaehler<6> 
  4: DATA<3>            9: FahrSpeicher2<5>.LFBK  14: FahrZaehler<7> 
  5: DATA<4>           10: FahrSpeicher2<6>.LFBK  15: Mcompar__cmp_gt0001_AGB32/Mcompar__cmp_gt0001_AGB32_D2 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
EndV2                ........XXXXXXX......................... 7       7
FahrSpeicher2<7>     .......X................................ 1       1
FahrSpeicher2<6>     ......X................................. 1       1
FahrSpeicher2<5>     .....X.................................. 1       1
FahrSpeicher2<4>     ....X................................... 1       1
FahrSpeicher2<3>     ...X.................................... 1       1
FahrSpeicher2<2>     ..X..................................... 1       1
FahrSpeicher2<1>     .X...................................... 1       1
FahrSpeicher2<0>     X....................................... 1       1
FahrSpeicher1<7>     .......X................................ 1       1
FahrSpeicher1<6>     ......X................................. 1       1
FahrSpeicher1<5>     .....X.................................. 1       1
FahrSpeicher1<4>     ....X................................... 1       1
FahrSpeicher1<3>     ...X.................................... 1       1
FahrSpeicher1<2>     ..X..................................... 1       1
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********













FDCPE_EndV1: FDCPE port map (EndV1,EXP1_.EXP,clkLatch1,rst,'0');

FDCPE_EndV2: FDCPE port map (EndV2,EndV2_D,clkLatch2,rst,'0');
EndV2_D <= ((
	NOT Mcompar__cmp_gt0001_AGB32/Mcompar__cmp_gt0001_AGB32_D2)
	OR (EXP4_.EXP)
	OR (EXP5_.EXP)
	OR (FahrZaehler(7) AND NOT FahrSpeicher2(7).LFBK)
	OR (FahrZaehler(6) AND FahrZaehler(7) AND 
	NOT FahrSpeicher2(6).LFBK)
	OR (FahrZaehler(6) AND NOT FahrSpeicher2(7).LFBK AND 
	NOT FahrSpeicher2(6).LFBK)
	OR (FahrZaehler(5) AND NOT FahrSpeicher2(7).LFBK AND 
	NOT FahrSpeicher2(6).LFBK AND NOT FahrSpeicher2(5).LFBK));

FDCPE_FahrSpeicher10: FDCPE port map (FahrSpeicher1(0),DATA(0),clkLatch1,rst,'0');

FDCPE_FahrSpeicher11: FDCPE port map (FahrSpeicher1(1),DATA(1),clkLatch1,rst,'0');

FDCPE_FahrSpeicher12: FDCPE port map (FahrSpeicher1(2),DATA(2),clkLatch1,rst,'0');

FDCPE_FahrSpeicher13: FDCPE port map (FahrSpeicher1(3),DATA(3),clkLatch1,rst,'0');

FDCPE_FahrSpeicher14: FDCPE port map (FahrSpeicher1(4),DATA(4),clkLatch1,rst,'0');

FDCPE_FahrSpeicher15: FDCPE port map (FahrSpeicher1(5),DATA(5),clkLatch1,rst,'0');

FDCPE_FahrSpeicher16: FDCPE port map (FahrSpeicher1(6),DATA(6),clkLatch1,rst,'0');

FDCPE_FahrSpeicher17: FDCPE port map (FahrSpeicher1(7),DATA(7),clkLatch1,rst,'0');

FDCPE_FahrSpeicher20: FDCPE port map (FahrSpeicher2(0),DATA(0),clkLatch2,rst,'0');

FDCPE_FahrSpeicher21: FDCPE port map (FahrSpeicher2(1),DATA(1),clkLatch2,rst,'0');

FDCPE_FahrSpeicher22: FDCPE port map (FahrSpeicher2(2),DATA(2),clkLatch2,rst,'0');

FDCPE_FahrSpeicher23: FDCPE port map (FahrSpeicher2(3),DATA(3),clkLatch2,rst,'0');

FDCPE_FahrSpeicher24: FDCPE port map (FahrSpeicher2(4),DATA(4),clkLatch2,rst,'0');

FDCPE_FahrSpeicher25: FDCPE port map (FahrSpeicher2(5),DATA(5),clkLatch2,rst,'0');

FDCPE_FahrSpeicher26: FDCPE port map (FahrSpeicher2(6),DATA(6),clkLatch2,rst,'0');

FDCPE_FahrSpeicher27: FDCPE port map (FahrSpeicher2(7),DATA(7),clkLatch2,rst,'0');

FTCPE_FahrZaehler0: FTCPE port map (FahrZaehler(0),'1',clk,rst,'0');

FTCPE_FahrZaehler1: FTCPE port map (FahrZaehler(1),FahrZaehler(0).LFBK,clk,rst,'0');

FTCPE_FahrZaehler2: FTCPE port map (FahrZaehler(2),FahrZaehler_T(2),clk,rst,'0');
FahrZaehler_T(2) <= (FahrZaehler(1).LFBK AND FahrZaehler(0).LFBK);

FTCPE_FahrZaehler3: FTCPE port map (FahrZaehler(3),FahrZaehler_T(3),clk,rst,'0');
FahrZaehler_T(3) <= (FahrZaehler(1).LFBK AND FahrZaehler(2).LFBK AND 
	FahrZaehler(0).LFBK);

FTCPE_FahrZaehler4: FTCPE port map (FahrZaehler(4),FahrZaehler_T(4),clk,rst,'0');
FahrZaehler_T(4) <= (FahrZaehler(1).LFBK AND FahrZaehler(2).LFBK AND 
	FahrZaehler(3).LFBK AND FahrZaehler(0).LFBK);

FTCPE_FahrZaehler5: FTCPE port map (FahrZaehler(5),FahrZaehler_T(5),clk,rst,'0');
FahrZaehler_T(5) <= (FahrZaehler(1).LFBK AND FahrZaehler(2).LFBK AND 
	FahrZaehler(3).LFBK AND FahrZaehler(0).LFBK AND FahrZaehler(4).LFBK);

FTCPE_FahrZaehler6: FTCPE port map (FahrZaehler(6),FahrZaehler_T(6),clk,rst,'0');
FahrZaehler_T(6) <= (FahrZaehler(1).LFBK AND FahrZaehler(2).LFBK AND 
	FahrZaehler(3).LFBK AND FahrZaehler(0).LFBK AND FahrZaehler(4).LFBK AND 
	FahrZaehler(5).LFBK);

FTCPE_FahrZaehler7: FTCPE port map (FahrZaehler(7),FahrZaehler_T(7),clk,rst,'0');
FahrZaehler_T(7) <= (FahrZaehler(1).LFBK AND FahrZaehler(2).LFBK AND 
	FahrZaehler(3).LFBK AND FahrZaehler(0).LFBK AND FahrZaehler(4).LFBK AND 
	FahrZaehler(5).LFBK AND FahrZaehler(6).LFBK);


Mcompar__cmp_gt0000_AGB32/Mcompar__cmp_gt0000_AGB32_D2 <= ((EXP0_.EXP)
	OR (EndV1_OBUF.EXP)
	OR (FahrSpeicher1(4) AND NOT FahrZaehler(4).LFBK)
	OR (FahrSpeicher1(6) AND NOT FahrZaehler(6).LFBK)
	OR (FahrSpeicher1(7) AND NOT FahrZaehler(7).LFBK)
	OR (FahrSpeicher1(5) AND NOT FahrZaehler(5).LFBK)
	OR (FahrSpeicher1(3) AND NOT $OpTx$$OpTx$FX_DC$3_INV$311 AND 
	NOT FahrZaehler(3).LFBK));


Mcompar__cmp_gt0001_AGB32/Mcompar__cmp_gt0001_AGB32_D2 <= ((EXP2_.EXP)
	OR (EXP3_.EXP)
	OR (FahrSpeicher2(4) AND NOT FahrZaehler(4).LFBK)
	OR (FahrSpeicher2(6) AND NOT FahrZaehler(6).LFBK)
	OR (FahrSpeicher2(7) AND NOT FahrZaehler(7).LFBK)
	OR (FahrSpeicher2(5) AND NOT FahrZaehler(5).LFBK)
	OR (FahrSpeicher2(3) AND NOT $OpTx$$OpTx$FX_DC$4_INV$312 AND 
	NOT FahrZaehler(3).LFBK));

Register Legend:
 FDCPE (Q,D,C,CLR,PRE); 
 FTCPE (Q,D,C,CLR,PRE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC9572-7-PC84


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 | 31                                                          55 | 
 | 32                                                          54 | 
 \ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 /
   --------------------------------------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 TIE                              43 TIE                           
  2 TIE                              44 DATA<0>                       
  3 TIE                              45 TIE                           
  4 TIE                              46 TIE                           
  5 DATA<4>                          47 TIE                           
  6 TIE                              48 TIE                           
  7 TIE                              49 GND                           
  8 GND                              50 TIE                           
  9 clkLatch1                        51 EndV2                         
 10 clkLatch2                        52 TIE                           
 11 TIE                              53 DATA<5>                       
 12 clk                              54 TIE                           
 13 TIE                              55 TIE                           
 14 TIE                              56 TIE                           
 15 TIE                              57 TIE                           
 16 GND                              58 TIE                           
 17 DATA<7>                          59 TDO                           
 18 TIE                              60 GND                           
 19 TIE                              61 TIE                           
 20 TIE                              62 TIE                           
 21 TIE                              63 TIE                           
 22 VCC                              64 VCC                           
 23 TIE                              65 TIE                           
 24 TIE                              66 TIE                           
 25 TIE                              67 TIE                           
 26 TIE                              68 TIE                           
 27 GND                              69 TIE                           
 28 TDI                              70 DATA<3>                       
 29 TMS                              71 TIE                           
 30 TCK                              72 DATA<1>                       
 31 EndV1                            73 VCC                           
 32 TIE                              74 rst                           
 33 TIE                              75 TIE                           
 34 TIE                              76 TIE                           
 35 TIE                              77 TIE                           
 36 TIE                              78 VCC                           
 37 DATA<2>                          79 TIE                           
 38 VCC                              80 TIE                           
 39 TIE                              81 TIE                           
 40 TIE                              82 TIE                           
 41 TIE                              83 DATA<6>                       
 42 GND                              84 TIE                           


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc9572-7-PC84
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : STD
Ground on Unused IOs                        : OFF
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
FASTConnect/UIM optimzation                 : ON
Local Feedback                              : ON
Pin Feedback                                : ON
Input Limit                                 : 36
Pterm Limit                                 : 25
