---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 12:34:48 03/06/2007 -- Design Name: -- Module Name: EndTreiber - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity EndTreiber is Port ( DATA : inout STD_LOGIC_VECTOR (7 downto 0); FahrCount : in STD_LOGIC_VECTOR (7 downto 0); ADR : in STD_LOGIC_VECTOR (2 downto 0); clk : in STD_LOGIC; rst : in STD_LOGIC; IOSEL : in STD_LOGIC; RW : in STD_LOGIC; CLK10KHz : in STD_LOGIC; Sbg01 : in STD_LOGIC; EndR01 : out STD_LOGIC; EndL01 : out STD_LOGIC); end EndTreiber; architecture Behavioral of EndTreiber is signal FahrSpeicher01 : std_logic_vector(7 downto 0); -- FahrLogic...(0) = E/A -- FahrLogic...(1) = V/R -- FahrLogic...(2) = Licht signal FahrLogic01 : std_logic_vector(2 downto 0); signal SBG_01 : std_logic; -- signal rst_11 : std_logic; -- begin -- rst_11 <= rst or Sbg01; -- -- FF Fahrstufe Ansteuerung Links / Rechts process(clk, rst_11, Clk10KHz, Sbg01, FahrLogic01, FahrSpeicher01, FahrCount) begin -- IF rst_11 = '1' then EndL01 <= '0'; EndR01 <= '0'; ELSIF rising_edge(clk) THEN -- IF FahrSpeicher01 > FahrCount THEN -- if FahrCount = 0 then if Sbg01 = '1' and FahrLogic01(0) = '1' and FahrLogic01(1) = '1' then EndR01 <= '1'; else EndR01 <= '0'; end if ; -- if Sbg01 = '1' and FahrLogic01(0) = '1' and FahrLogic01(1) = '0' then EndL01 <= '1'; else EndL01 <= '0'; end if ; -- -- elsif FahrCount = FahrSpeicher01 then ELSE if Sbg01 = '1' and Clk10KHz = '1' and FahrLogic01(2) = '1' then EndR01 <= '1'; else EndR01 <= '0'; end if; -- if Sbg01 = '1' and Clk10KHz = '1' and FahrLogic01(2) = '0' then EndL01 <= '1'; else EndL01 <= '0'; end if; -- end if; -- EndR01 <= (((COMP_01 AND FahrLogic01(0)) or ((NOT COMP_01) and FahrLogic01(2) -- and Clk10KHz)) and Sbg01 and FahrLogic01(1)); -- EndL01 <= (((COMP_01 AND FahrLogic01(0)) or ((NOT COMP_01) and FahrLogic01(2) -- and Clk10KHz)) and Sbg01 and (NOT FahrLogic01(1))); -- END IF; end process; -- 8-Bit Latch Geschwindigkeit process(rst_11, DATA, ADR, IOSEL, RW) begin IF rst_11 = '1' THEN FahrSpeicher01 <= "00000000"; ELSIF (ADR = "000" AND IOSEL = '0' AND RW = '0') then FahrSpeicher01 <= DATA; END IF; end process; -- 8/3-Bit Latch Logic process(clk, rst_11, DATA, ADR, IOSEL, RW) begin if rst_11 = '1' then FahrLogic01 <= "000"; elsif (ADR = "001" AND IOSEL = '0' AND RW = '0') then FahrLogic01 <= DATA(2 downto 0); end if; end process; -- Strombegrenzung Speicher Logic process(clk, rst, ADR, IOSEL, RW, Sbg01, SBG_01) begin if rst = '1' then SBG_01 <= '0'; elsif rising_edge(clk) then SBG_01 <= Sbg01; end if; if ADR = "101" AND IOSEL = '0' AND RW = '1' then DATA(0) <= SBG_01; else DATA(0) <= 'Z'; end if; end process; end Behavioral;