ISR (USART0_RX_vect)						// Receiver buffer is full
{
	unsigned char i = 0;
	UCSR0B &= ~(1<<RXCIE0);					// disable receive complete interrupt
	rc_array[i] = UDR0;						// store first byte
	PORTA ^= (1<<PA5);						// toggle A5
	i++;
	while (!(UCSR0A & (1<<RXC0)))			// wait receive register is full
	{
		rc_array[i] = UDR0;					// store second byte
//		PORTA ^= (1<<PA5);				// toggle A5
	}
	i++;
	for (i=2;i<=rc_array[1];i++)
	{
		while (!(UCSR0A & (1<<RXC0)))			// wait receive register is full
		{
			rc_array[i] = UDR0;					// store second byte
			//		PORTA ^= (1<<PA5);				// toggle A5
		}
	}
	UCSR0B |= (1<<RXCIE0);					// enable receive complete interrupt
	flags.nd = 1;
}