library ieee; use ieee.std_logic_1164.all; entity Dual_AND_Gate is port( A : in std_logic; B : in std_logic; Y : out std_logic); end Dual_AND_Gate; architecture behavioral of Dual_AND_Gate is begin Y <= A AND B; end behavioral; ---- library ieee; use ieee.std_logic_1164.all; entity Dual_OR_Gate is port( A : in std_logic; B : in std_logic; Y : out std_logic); end Dual_OR_Gate; architecture behavioral of Dual_OR_Gate is begin Y <= A OR B; end behavioral; ---- library ieee; use ieee.std_logic_1164.all; entity NOT_Gate is port( I : in std_logic; O : out std_logic); end NOT_Gate; architecture behavioral of NOT_Gate is begin O <= NOT I; end behavioral; ---- library ieee; use ieee.std_logic_1164.all; entity Dual_XOR_Gate is port( A : in std_logic; B : in std_logic; Y : out std_logic); end Dual_XOR_Gate; architecture behavioral of Dual_XOR_Gate is component Dual_AND_Gate is port ( A : in std_logic; B : in std_logic; Y : out std_logic); end component; component Dual_OR_Gate is port ( A : in std_logic; B : in std_logic; Y : out std_logic); end component; component NOT_Gate is port ( I : in std_logic; O : out std_logic); end component; signal An : std_logic; signal Bn : std_logic; signal M : std_logic; signal N : std_logic; begin NICHT1 : NOT_Gate port map ( I => A, O => An); NICHT2 : NOT_Gate port map ( I => B, O => Bn); UND1 : Dual_AND_Gate port map ( A => A, B => Bn, Y => N); UND2 : Dual_AND_Gate port map ( A => An, B => B, Y => M); ODER : Dual_OR_Gate port map ( A => M, B => N, Y => Y); end behavioral; ---- library ieee; use ieee.std_logic_1164.all; entity logik is port( sw0 : in std_logic; sw1 : in std_logic; sw2 : in std_logic; sw3 : in std_logic; led : out std_logic ); end logik; architecture behavioral of logik is component Dual_AND_Gate is port ( A : in std_logic; B : in std_logic; Y : out std_logic); end component; component Dual_XOR_Gate is port ( A : in std_logic; B : in std_logic; Y : out std_logic); end component; signal sig1 :std_logic; signal sig2 :std_logic; begin UND1 : Dual_AND_Gate port map ( A => sw0, B => sw1, Y => sig1); UND2 : Dual_AND_Gate port map ( A => sw2, B => sw3, Y => sig2); XOR1 : Dual_XOR_Gate port map ( A => sig1, B => sig2, Y => led); end behavioral;