Static Timing Analysis

Project : UART_Bootloader
Build Time : 11/26/14 11:48:56
Device : CY8C4245AXI-483
Temperature : -40C - 85C
VDDA : 5.00
VDDD : 5.00
Voltage : 5
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
Clock(FFB) Clock(FFB) 20.000 kHz 20.000 kHz N/A
CyHFCLK CyHFCLK 24.000 MHz 24.000 MHz N/A
UART_SCBCLK CyHFCLK 1.412 MHz 1.412 MHz N/A
Clock CyHFCLK 20.000 kHz 20.000 kHz N/A
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyLFCLK CyLFCLK 32.000 kHz 32.000 kHz N/A
CySYSCLK CySYSCLK 24.000 MHz 24.000 MHz N/A
UART_SCBCLK(FFB) UART_SCBCLK(FFB) 1.412 MHz 1.412 MHz N/A
+ Clock To Output Section
+ Clock(FFB)
Source Destination Delay (ns)
\PWM:cy_m0s8_tcpwm_1\/line_out P1_6(0)_PAD 21.115
Type Location Fanout Instance/Net Source Dest Delay (ns)
m0s8tcpwmcell F(TCPWM,0) 1 \PWM:cy_m0s8_tcpwm_1\ \PWM:cy_m0s8_tcpwm_1\/clock \PWM:cy_m0s8_tcpwm_1\/line_out 0.000
Route 1 Net_29 \PWM:cy_m0s8_tcpwm_1\/line_out P1_6(0)/pin_input 5.695
iocell2 P1[6] 1 P1_6(0) P1_6(0)/pin_input P1_6(0)/pad_out 15.420
Route 1 P1_6(0)_PAD P1_6(0)/pad_out P1_6(0)_PAD 0.000
Clock Clock path delay 0.000