-------------------------------------------------------------------------------- Release 14.7 Trace (nt64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf main.ucf Design file: main.ncd Physical constraint file: main.pcf Device,package,speed: xc6vlx75t,ff784,C,-2 (PRODUCTION 1.17 2013-10-13) Report level: verbose report Environment Variable Effect -------------------- ------ NONE No environment variables were set -------------------------------------------------------------------------------- INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612). INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet. ================================================================================ Timing constraint: TS_evb_ref_clk_p = PERIOD TIMEGRP "evb_ref_clk_p" 100 MHz LOW 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 component switching limit errors) Minimum period is 4.000ns. -------------------------------------------------------------------------------- Component Switching Limit Checks: TS_evb_ref_clk_p = PERIOD TIMEGRP "evb_ref_clk_p" 100 MHz LOW 50%; -------------------------------------------------------------------------------- Slack: 6.000ns (period - (min low pulse limit / (low pulse / period))) Period: 10.000ns Low pulse: 5.000ns Low pulse limit: 2.000ns (Tdcmpw_CLKIN_100_150) Physical resource: System_clk_management/clk_mgmt/CLKIN1 Logical resource: System_clk_management/clk_mgmt/CLKIN1 Location pin: MMCM_ADV_X0Y0.CLKIN1 Clock network: System_clk_management/sys_clk_reg -------------------------------------------------------------------------------- Slack: 6.000ns (period - (min high pulse limit / (high pulse / period))) Period: 10.000ns High pulse: 5.000ns High pulse limit: 2.000ns (Tdcmpw_CLKIN_100_150) Physical resource: System_clk_management/clk_mgmt/CLKIN1 Logical resource: System_clk_management/clk_mgmt/CLKIN1 Location pin: MMCM_ADV_X0Y0.CLKIN1 Clock network: System_clk_management/sys_clk_reg -------------------------------------------------------------------------------- Slack: 8.668ns (period - min period limit) Period: 10.000ns Min period limit: 1.332ns (750.751MHz) (Tmmcmper_CLKIN(Finmax)) Physical resource: System_clk_management/clk_mgmt/CLKIN1 Logical resource: System_clk_management/clk_mgmt/CLKIN1 Location pin: MMCM_ADV_X0Y0.CLKIN1 Clock network: System_clk_management/sys_clk_reg -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_DCO1_p = PERIOD TIMEGRP "DCO1_p" 195 MHz HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 component switching limit errors) Minimum period is 1.333ns. -------------------------------------------------------------------------------- Component Switching Limit Checks: TS_DCO1_p = PERIOD TIMEGRP "DCO1_p" 195 MHz HIGH 50%; -------------------------------------------------------------------------------- Slack: 3.795ns (period - min period limit) Period: 5.128ns Min period limit: 1.333ns (750.188MHz) (Tbcper_I) Physical resource: AD9249_dig_data_interface/DCO_1_BUFG/I0 Logical resource: AD9249_dig_data_interface/DCO_1_BUFG/I0 Location pin: BUFGCTRL_X0Y30.I0 Clock network: debug_header_14_OBUF -------------------------------------------------------------------------------- Slack: 3.814ns (period - min period limit) Period: 5.128ns Min period limit: 1.314ns (761.035MHz) (Tickper) Physical resource: AD9249_dig_data_interface/ADC_bank1/fco_data_nib<1>/CLK Logical resource: AD9249_dig_data_interface/ADC_bank1/FCO_DDR/iddr_inst/CK Location pin: ILOGIC_X2Y117.CLK Clock network: AD9249_dig_data_interface/DCO_1_BUFG -------------------------------------------------------------------------------- Slack: 3.814ns (period - min period limit) Period: 5.128ns Min period limit: 1.314ns (761.035MHz) (Tickper) Physical resource: AD9249_dig_data_interface/ADC_bank1/fco_data_nib<1>/CLKB Logical resource: AD9249_dig_data_interface/ADC_bank1/FCO_DDR/iddr_inst/CKB Location pin: ILOGIC_X2Y117.CLKB Clock network: AD9249_dig_data_interface/DCO_1_BUFG -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_DCO1_n = PERIOD TIMEGRP "DCO1_n" 195 MHz HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 1476 paths analyzed, 703 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) Minimum period is 3.915ns. -------------------------------------------------------------------------------- Paths for end point AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0_10 (SLICE_X36Y53.C4), 9 paths -------------------------------------------------------------------------------- Slack (setup path): 1.213ns (requirement - (data path - clock path skew + uncertainty)) Source: AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[1].ADC_channelXX_create_frame/Generate_frame/d_ack (FF) Destination: AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0_10 (FF) Requirement: 5.128ns Data Path Delay: 3.577ns (Levels of Logic = 3) Clock Path Skew: -0.303ns (1.262 - 1.565) Source Clock: AD9249_dig_data_interface/DCO_1_BUFG rising at 0.000ns Destination Clock: AD9249_dig_data_interface/DCO_1_BUFG rising at 5.128ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[1].ADC_channelXX_create_frame/Generate_frame/d_ack to AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0_10 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X38Y84.BQ Tcko 0.283 AD9249_dig_data_interface/bank1_data_ack_vector_DCO1_reg<3> AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[1].ADC_channelXX_create_frame/Generate_frame/d_ack SLICE_X37Y84.A2 net (fanout=2) 0.533 AD9249_dig_data_interface/bank1_data_ack_vector_DCO1_reg<1> SLICE_X37Y84.A Tilo 0.061 AD9249_dig_data_interface/bank1_data_frm_matrix_read_DCO1 AD9249_dig_data_interface/_n0306_inv_SW0 SLICE_X36Y87.B1 net (fanout=1) 0.642 AD9249_dig_data_interface/N6 SLICE_X36Y87.B Tilo 0.061 AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_2<2> AD9249_dig_data_interface/_n0306_inv_rstpot SLICE_X36Y53.C4 net (fanout=96) 1.976 AD9249_dig_data_interface/_n0306_inv_rstpot SLICE_X36Y53.CLK Tas 0.021 AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0<11> AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0_10_dpot AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0_10 ------------------------------------------------- --------------------------- Total 3.577ns (0.426ns logic, 3.151ns route) (11.9% logic, 88.1% route) -------------------------------------------------------------------------------- Slack (setup path): 1.296ns (requirement - (data path - clock path skew + uncertainty)) Source: AD9249_dig_data_interface/bank1_data_frm_matrix_set_DCO1 (FF) Destination: AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0_10 (FF) Requirement: 5.128ns Data Path Delay: 3.497ns (Levels of Logic = 3) Clock Path Skew: -0.300ns (1.262 - 1.562) Source Clock: AD9249_dig_data_interface/DCO_1_BUFG rising at 0.000ns Destination Clock: AD9249_dig_data_interface/DCO_1_BUFG rising at 5.128ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: AD9249_dig_data_interface/bank1_data_frm_matrix_set_DCO1 to AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0_10 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X36Y84.AQ Tcko 0.322 AD9249_dig_data_interface/bank1_data_frm_matrix_set_DCO1 AD9249_dig_data_interface/bank1_data_frm_matrix_set_DCO1 SLICE_X37Y84.A3 net (fanout=4) 0.414 AD9249_dig_data_interface/bank1_data_frm_matrix_set_DCO1 SLICE_X37Y84.A Tilo 0.061 AD9249_dig_data_interface/bank1_data_frm_matrix_read_DCO1 AD9249_dig_data_interface/_n0306_inv_SW0 SLICE_X36Y87.B1 net (fanout=1) 0.642 AD9249_dig_data_interface/N6 SLICE_X36Y87.B Tilo 0.061 AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_2<2> AD9249_dig_data_interface/_n0306_inv_rstpot SLICE_X36Y53.C4 net (fanout=96) 1.976 AD9249_dig_data_interface/_n0306_inv_rstpot SLICE_X36Y53.CLK Tas 0.021 AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0<11> AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0_10_dpot AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0_10 ------------------------------------------------- --------------------------- Total 3.497ns (0.465ns logic, 3.032ns route) (13.3% logic, 86.7% route) -------------------------------------------------------------------------------- Slack (setup path): 1.383ns (requirement - (data path - clock path skew + uncertainty)) Source: AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[2].ADC_channelXX_create_frame/Generate_frame/d_ack (FF) Destination: AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0_10 (FF) Requirement: 5.128ns Data Path Delay: 3.407ns (Levels of Logic = 3) Clock Path Skew: -0.303ns (1.262 - 1.565) Source Clock: AD9249_dig_data_interface/DCO_1_BUFG rising at 0.000ns Destination Clock: AD9249_dig_data_interface/DCO_1_BUFG rising at 5.128ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[2].ADC_channelXX_create_frame/Generate_frame/d_ack to AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0_10 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X38Y84.CQ Tcko 0.283 AD9249_dig_data_interface/bank1_data_ack_vector_DCO1_reg<3> AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[2].ADC_channelXX_create_frame/Generate_frame/d_ack SLICE_X37Y84.A4 net (fanout=2) 0.363 AD9249_dig_data_interface/bank1_data_ack_vector_DCO1_reg<2> SLICE_X37Y84.A Tilo 0.061 AD9249_dig_data_interface/bank1_data_frm_matrix_read_DCO1 AD9249_dig_data_interface/_n0306_inv_SW0 SLICE_X36Y87.B1 net (fanout=1) 0.642 AD9249_dig_data_interface/N6 SLICE_X36Y87.B Tilo 0.061 AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_2<2> AD9249_dig_data_interface/_n0306_inv_rstpot SLICE_X36Y53.C4 net (fanout=96) 1.976 AD9249_dig_data_interface/_n0306_inv_rstpot SLICE_X36Y53.CLK Tas 0.021 AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0<11> AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0_10_dpot AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0_10 ------------------------------------------------- --------------------------- Total 3.407ns (0.426ns logic, 2.981ns route) (12.5% logic, 87.5% route) -------------------------------------------------------------------------------- Paths for end point AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0_9 (SLICE_X36Y53.B4), 9 paths -------------------------------------------------------------------------------- Slack (setup path): 1.217ns (requirement - (data path - clock path skew + uncertainty)) Source: AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[1].ADC_channelXX_create_frame/Generate_frame/d_ack (FF) Destination: AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0_9 (FF) Requirement: 5.128ns Data Path Delay: 3.573ns (Levels of Logic = 3) Clock Path Skew: -0.303ns (1.262 - 1.565) Source Clock: AD9249_dig_data_interface/DCO_1_BUFG rising at 0.000ns Destination Clock: AD9249_dig_data_interface/DCO_1_BUFG rising at 5.128ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[1].ADC_channelXX_create_frame/Generate_frame/d_ack to AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0_9 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X38Y84.BQ Tcko 0.283 AD9249_dig_data_interface/bank1_data_ack_vector_DCO1_reg<3> AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[1].ADC_channelXX_create_frame/Generate_frame/d_ack SLICE_X37Y84.A2 net (fanout=2) 0.533 AD9249_dig_data_interface/bank1_data_ack_vector_DCO1_reg<1> SLICE_X37Y84.A Tilo 0.061 AD9249_dig_data_interface/bank1_data_frm_matrix_read_DCO1 AD9249_dig_data_interface/_n0306_inv_SW0 SLICE_X36Y87.B1 net (fanout=1) 0.642 AD9249_dig_data_interface/N6 SLICE_X36Y87.B Tilo 0.061 AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_2<2> AD9249_dig_data_interface/_n0306_inv_rstpot SLICE_X36Y53.B4 net (fanout=96) 1.974 AD9249_dig_data_interface/_n0306_inv_rstpot SLICE_X36Y53.CLK Tas 0.019 AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0<11> AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0_9_dpot AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0_9 ------------------------------------------------- --------------------------- Total 3.573ns (0.424ns logic, 3.149ns route) (11.9% logic, 88.1% route) -------------------------------------------------------------------------------- Slack (setup path): 1.300ns (requirement - (data path - clock path skew + uncertainty)) Source: AD9249_dig_data_interface/bank1_data_frm_matrix_set_DCO1 (FF) Destination: AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0_9 (FF) Requirement: 5.128ns Data Path Delay: 3.493ns (Levels of Logic = 3) Clock Path Skew: -0.300ns (1.262 - 1.562) Source Clock: AD9249_dig_data_interface/DCO_1_BUFG rising at 0.000ns Destination Clock: AD9249_dig_data_interface/DCO_1_BUFG rising at 5.128ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: AD9249_dig_data_interface/bank1_data_frm_matrix_set_DCO1 to AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0_9 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X36Y84.AQ Tcko 0.322 AD9249_dig_data_interface/bank1_data_frm_matrix_set_DCO1 AD9249_dig_data_interface/bank1_data_frm_matrix_set_DCO1 SLICE_X37Y84.A3 net (fanout=4) 0.414 AD9249_dig_data_interface/bank1_data_frm_matrix_set_DCO1 SLICE_X37Y84.A Tilo 0.061 AD9249_dig_data_interface/bank1_data_frm_matrix_read_DCO1 AD9249_dig_data_interface/_n0306_inv_SW0 SLICE_X36Y87.B1 net (fanout=1) 0.642 AD9249_dig_data_interface/N6 SLICE_X36Y87.B Tilo 0.061 AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_2<2> AD9249_dig_data_interface/_n0306_inv_rstpot SLICE_X36Y53.B4 net (fanout=96) 1.974 AD9249_dig_data_interface/_n0306_inv_rstpot SLICE_X36Y53.CLK Tas 0.019 AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0<11> AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0_9_dpot AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0_9 ------------------------------------------------- --------------------------- Total 3.493ns (0.463ns logic, 3.030ns route) (13.3% logic, 86.7% route) -------------------------------------------------------------------------------- Slack (setup path): 1.387ns (requirement - (data path - clock path skew + uncertainty)) Source: AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[2].ADC_channelXX_create_frame/Generate_frame/d_ack (FF) Destination: AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0_9 (FF) Requirement: 5.128ns Data Path Delay: 3.403ns (Levels of Logic = 3) Clock Path Skew: -0.303ns (1.262 - 1.565) Source Clock: AD9249_dig_data_interface/DCO_1_BUFG rising at 0.000ns Destination Clock: AD9249_dig_data_interface/DCO_1_BUFG rising at 5.128ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[2].ADC_channelXX_create_frame/Generate_frame/d_ack to AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0_9 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X38Y84.CQ Tcko 0.283 AD9249_dig_data_interface/bank1_data_ack_vector_DCO1_reg<3> AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[2].ADC_channelXX_create_frame/Generate_frame/d_ack SLICE_X37Y84.A4 net (fanout=2) 0.363 AD9249_dig_data_interface/bank1_data_ack_vector_DCO1_reg<2> SLICE_X37Y84.A Tilo 0.061 AD9249_dig_data_interface/bank1_data_frm_matrix_read_DCO1 AD9249_dig_data_interface/_n0306_inv_SW0 SLICE_X36Y87.B1 net (fanout=1) 0.642 AD9249_dig_data_interface/N6 SLICE_X36Y87.B Tilo 0.061 AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_2<2> AD9249_dig_data_interface/_n0306_inv_rstpot SLICE_X36Y53.B4 net (fanout=96) 1.974 AD9249_dig_data_interface/_n0306_inv_rstpot SLICE_X36Y53.CLK Tas 0.019 AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0<11> AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0_9_dpot AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0_9 ------------------------------------------------- --------------------------- Total 3.403ns (0.424ns logic, 2.979ns route) (12.5% logic, 87.5% route) -------------------------------------------------------------------------------- Paths for end point AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0_11 (SLICE_X36Y53.D6), 9 paths -------------------------------------------------------------------------------- Slack (setup path): 1.357ns (requirement - (data path - clock path skew + uncertainty)) Source: AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[1].ADC_channelXX_create_frame/Generate_frame/d_ack (FF) Destination: AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0_11 (FF) Requirement: 5.128ns Data Path Delay: 3.433ns (Levels of Logic = 3) Clock Path Skew: -0.303ns (1.262 - 1.565) Source Clock: AD9249_dig_data_interface/DCO_1_BUFG rising at 0.000ns Destination Clock: AD9249_dig_data_interface/DCO_1_BUFG rising at 5.128ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[1].ADC_channelXX_create_frame/Generate_frame/d_ack to AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0_11 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X38Y84.BQ Tcko 0.283 AD9249_dig_data_interface/bank1_data_ack_vector_DCO1_reg<3> AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[1].ADC_channelXX_create_frame/Generate_frame/d_ack SLICE_X37Y84.A2 net (fanout=2) 0.533 AD9249_dig_data_interface/bank1_data_ack_vector_DCO1_reg<1> SLICE_X37Y84.A Tilo 0.061 AD9249_dig_data_interface/bank1_data_frm_matrix_read_DCO1 AD9249_dig_data_interface/_n0306_inv_SW0 SLICE_X36Y87.B1 net (fanout=1) 0.642 AD9249_dig_data_interface/N6 SLICE_X36Y87.B Tilo 0.061 AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_2<2> AD9249_dig_data_interface/_n0306_inv_rstpot SLICE_X36Y53.D6 net (fanout=96) 1.834 AD9249_dig_data_interface/_n0306_inv_rstpot SLICE_X36Y53.CLK Tas 0.019 AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0<11> AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0_11_dpot AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0_11 ------------------------------------------------- --------------------------- Total 3.433ns (0.424ns logic, 3.009ns route) (12.4% logic, 87.6% route) -------------------------------------------------------------------------------- Slack (setup path): 1.440ns (requirement - (data path - clock path skew + uncertainty)) Source: AD9249_dig_data_interface/bank1_data_frm_matrix_set_DCO1 (FF) Destination: AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0_11 (FF) Requirement: 5.128ns Data Path Delay: 3.353ns (Levels of Logic = 3) Clock Path Skew: -0.300ns (1.262 - 1.562) Source Clock: AD9249_dig_data_interface/DCO_1_BUFG rising at 0.000ns Destination Clock: AD9249_dig_data_interface/DCO_1_BUFG rising at 5.128ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: AD9249_dig_data_interface/bank1_data_frm_matrix_set_DCO1 to AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0_11 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X36Y84.AQ Tcko 0.322 AD9249_dig_data_interface/bank1_data_frm_matrix_set_DCO1 AD9249_dig_data_interface/bank1_data_frm_matrix_set_DCO1 SLICE_X37Y84.A3 net (fanout=4) 0.414 AD9249_dig_data_interface/bank1_data_frm_matrix_set_DCO1 SLICE_X37Y84.A Tilo 0.061 AD9249_dig_data_interface/bank1_data_frm_matrix_read_DCO1 AD9249_dig_data_interface/_n0306_inv_SW0 SLICE_X36Y87.B1 net (fanout=1) 0.642 AD9249_dig_data_interface/N6 SLICE_X36Y87.B Tilo 0.061 AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_2<2> AD9249_dig_data_interface/_n0306_inv_rstpot SLICE_X36Y53.D6 net (fanout=96) 1.834 AD9249_dig_data_interface/_n0306_inv_rstpot SLICE_X36Y53.CLK Tas 0.019 AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0<11> AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0_11_dpot AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0_11 ------------------------------------------------- --------------------------- Total 3.353ns (0.463ns logic, 2.890ns route) (13.8% logic, 86.2% route) -------------------------------------------------------------------------------- Slack (setup path): 1.527ns (requirement - (data path - clock path skew + uncertainty)) Source: AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[2].ADC_channelXX_create_frame/Generate_frame/d_ack (FF) Destination: AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0_11 (FF) Requirement: 5.128ns Data Path Delay: 3.263ns (Levels of Logic = 3) Clock Path Skew: -0.303ns (1.262 - 1.565) Source Clock: AD9249_dig_data_interface/DCO_1_BUFG rising at 0.000ns Destination Clock: AD9249_dig_data_interface/DCO_1_BUFG rising at 5.128ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[2].ADC_channelXX_create_frame/Generate_frame/d_ack to AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0_11 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X38Y84.CQ Tcko 0.283 AD9249_dig_data_interface/bank1_data_ack_vector_DCO1_reg<3> AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[2].ADC_channelXX_create_frame/Generate_frame/d_ack SLICE_X37Y84.A4 net (fanout=2) 0.363 AD9249_dig_data_interface/bank1_data_ack_vector_DCO1_reg<2> SLICE_X37Y84.A Tilo 0.061 AD9249_dig_data_interface/bank1_data_frm_matrix_read_DCO1 AD9249_dig_data_interface/_n0306_inv_SW0 SLICE_X36Y87.B1 net (fanout=1) 0.642 AD9249_dig_data_interface/N6 SLICE_X36Y87.B Tilo 0.061 AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_2<2> AD9249_dig_data_interface/_n0306_inv_rstpot SLICE_X36Y53.D6 net (fanout=96) 1.834 AD9249_dig_data_interface/_n0306_inv_rstpot SLICE_X36Y53.CLK Tas 0.019 AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0<11> AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0_11_dpot AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_0_11 ------------------------------------------------- --------------------------- Total 3.263ns (0.424ns logic, 2.839ns route) (13.0% logic, 87.0% route) -------------------------------------------------------------------------------- Hold Paths: TS_DCO1_n = PERIOD TIMEGRP "DCO1_n" 195 MHz HIGH 50%; -------------------------------------------------------------------------------- Paths for end point AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_7_4 (SLICE_X37Y73.A6), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.094ns (requirement - (clock path skew + uncertainty - data path)) Source: AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[7].ADC_channelXX_create_frame/Generate_frame/d_frm_out_reg_4 (FF) Destination: AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_7_4 (FF) Requirement: 0.000ns Data Path Delay: 0.127ns (Levels of Logic = 1) Clock Path Skew: 0.033ns (0.467 - 0.434) Source Clock: AD9249_dig_data_interface/DCO_1_BUFG rising at 5.128ns Destination Clock: AD9249_dig_data_interface/DCO_1_BUFG rising at 5.128ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[7].ADC_channelXX_create_frame/Generate_frame/d_frm_out_reg_4 to AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_7_4 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X38Y73.AQ Tcko 0.098 AD9249_dig_data_interface/bank1_data_frm_matrix_DCO1_reg<7><7> AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[7].ADC_channelXX_create_frame/Generate_frame/d_frm_out_reg_4 SLICE_X37Y73.A6 net (fanout=1) 0.084 AD9249_dig_data_interface/bank1_data_frm_matrix_DCO1_reg<7><4> SLICE_X37Y73.CLK Tah (-Th) 0.055 AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_7<7> AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_7_4_dpot AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_7_4 ------------------------------------------------- --------------------------- Total 0.127ns (0.043ns logic, 0.084ns route) (33.9% logic, 66.1% route) -------------------------------------------------------------------------------- Paths for end point AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_6_4 (SLICE_X10Y97.A5), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.111ns (requirement - (clock path skew + uncertainty - data path)) Source: AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[6].ADC_channelXX_create_frame/Generate_frame/d_frm_out_reg_4 (FF) Destination: AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_6_4 (FF) Requirement: 0.000ns Data Path Delay: 0.147ns (Levels of Logic = 1) Clock Path Skew: 0.036ns (0.432 - 0.396) Source Clock: AD9249_dig_data_interface/DCO_1_BUFG rising at 5.128ns Destination Clock: AD9249_dig_data_interface/DCO_1_BUFG rising at 5.128ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[6].ADC_channelXX_create_frame/Generate_frame/d_frm_out_reg_4 to AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_6_4 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X13Y97.AQ Tcko 0.098 AD9249_dig_data_interface/bank1_data_frm_matrix_DCO1_reg<6><7> AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[6].ADC_channelXX_create_frame/Generate_frame/d_frm_out_reg_4 SLICE_X10Y97.A5 net (fanout=1) 0.125 AD9249_dig_data_interface/bank1_data_frm_matrix_DCO1_reg<6><4> SLICE_X10Y97.CLK Tah (-Th) 0.076 AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_6<7> AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_6_4_dpot AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_6_4 ------------------------------------------------- --------------------------- Total 0.147ns (0.022ns logic, 0.125ns route) (15.0% logic, 85.0% route) -------------------------------------------------------------------------------- Paths for end point AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_6_6 (SLICE_X10Y97.C5), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.111ns (requirement - (clock path skew + uncertainty - data path)) Source: AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[6].ADC_channelXX_create_frame/Generate_frame/d_frm_out_reg_6 (FF) Destination: AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_6_6 (FF) Requirement: 0.000ns Data Path Delay: 0.147ns (Levels of Logic = 1) Clock Path Skew: 0.036ns (0.432 - 0.396) Source Clock: AD9249_dig_data_interface/DCO_1_BUFG rising at 5.128ns Destination Clock: AD9249_dig_data_interface/DCO_1_BUFG rising at 5.128ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[6].ADC_channelXX_create_frame/Generate_frame/d_frm_out_reg_6 to AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_6_6 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X13Y97.CQ Tcko 0.098 AD9249_dig_data_interface/bank1_data_frm_matrix_DCO1_reg<6><7> AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[6].ADC_channelXX_create_frame/Generate_frame/d_frm_out_reg_6 SLICE_X10Y97.C5 net (fanout=1) 0.125 AD9249_dig_data_interface/bank1_data_frm_matrix_DCO1_reg<6><6> SLICE_X10Y97.CLK Tah (-Th) 0.076 AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_6<7> AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_6_6_dpot AD9249_dig_data_interface/bank1_data_frm_matrix_transfer_reg_6_6 ------------------------------------------------- --------------------------- Total 0.147ns (0.022ns logic, 0.125ns route) (15.0% logic, 85.0% route) -------------------------------------------------------------------------------- Component Switching Limit Checks: TS_DCO1_n = PERIOD TIMEGRP "DCO1_n" 195 MHz HIGH 50%; -------------------------------------------------------------------------------- Slack: 3.795ns (period - min period limit) Period: 5.128ns Min period limit: 1.333ns (750.188MHz) (Tbcper_I) Physical resource: AD9249_dig_data_interface/DCO_1_BUFG/I0 Logical resource: AD9249_dig_data_interface/DCO_1_BUFG/I0 Location pin: BUFGCTRL_X0Y30.I0 Clock network: debug_header_14_OBUF -------------------------------------------------------------------------------- Slack: 3.814ns (period - min period limit) Period: 5.128ns Min period limit: 1.314ns (761.035MHz) (Tickper) Physical resource: AD9249_dig_data_interface/ADC_bank1/fco_data_nib<1>/CLK Logical resource: AD9249_dig_data_interface/ADC_bank1/FCO_DDR/iddr_inst/CK Location pin: ILOGIC_X2Y117.CLK Clock network: AD9249_dig_data_interface/DCO_1_BUFG -------------------------------------------------------------------------------- Slack: 3.814ns (period - min period limit) Period: 5.128ns Min period limit: 1.314ns (761.035MHz) (Tickper) Physical resource: AD9249_dig_data_interface/ADC_bank1/fco_data_nib<1>/CLKB Logical resource: AD9249_dig_data_interface/ADC_bank1/FCO_DDR/iddr_inst/CKB Location pin: ILOGIC_X2Y117.CLKB Clock network: AD9249_dig_data_interface/DCO_1_BUFG -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_DCO2_p = PERIOD TIMEGRP "DCO2_p" 195 MHz HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 component switching limit errors) Minimum period is 1.333ns. -------------------------------------------------------------------------------- Component Switching Limit Checks: TS_DCO2_p = PERIOD TIMEGRP "DCO2_p" 195 MHz HIGH 50%; -------------------------------------------------------------------------------- Slack: 3.795ns (period - min period limit) Period: 5.128ns Min period limit: 1.333ns (750.188MHz) (Tbcper_I) Physical resource: AD9249_dig_data_interface/DCO_2_BUFG/I0 Logical resource: AD9249_dig_data_interface/DCO_2_BUFG/I0 Location pin: BUFGCTRL_X0Y31.I0 Clock network: AD9249_dig_data_interface/DCO_2 -------------------------------------------------------------------------------- Slack: 3.814ns (period - min period limit) Period: 5.128ns Min period limit: 1.314ns (761.035MHz) (Tickper) Physical resource: AD9249_dig_data_interface/ADC_bank2/fco_data_nib<1>/CLK Logical resource: AD9249_dig_data_interface/ADC_bank2/FCO_DDR/iddr_inst/CK Location pin: ILOGIC_X2Y95.CLK Clock network: AD9249_dig_data_interface/DCO_2_BUFG -------------------------------------------------------------------------------- Slack: 3.814ns (period - min period limit) Period: 5.128ns Min period limit: 1.314ns (761.035MHz) (Tickper) Physical resource: AD9249_dig_data_interface/ADC_bank2/fco_data_nib<1>/CLKB Logical resource: AD9249_dig_data_interface/ADC_bank2/FCO_DDR/iddr_inst/CKB Location pin: ILOGIC_X2Y95.CLKB Clock network: AD9249_dig_data_interface/DCO_2_BUFG -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_DCO2_n = PERIOD TIMEGRP "DCO2_n" 195 MHz HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 1476 paths analyzed, 703 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) Minimum period is 4.191ns. -------------------------------------------------------------------------------- Paths for end point AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1_6 (SLICE_X9Y91.C2), 9 paths -------------------------------------------------------------------------------- Slack (setup path): 0.937ns (requirement - (data path - clock path skew + uncertainty)) Source: AD9249_dig_data_interface/bank2_data_frm_matrix_set_DCO2 (FF) Destination: AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1_6 (FF) Requirement: 5.128ns Data Path Delay: 4.059ns (Levels of Logic = 3) Clock Path Skew: -0.097ns (1.326 - 1.423) Source Clock: AD9249_dig_data_interface/DCO_2_BUFG rising at 0.000ns Destination Clock: AD9249_dig_data_interface/DCO_2_BUFG rising at 5.128ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: AD9249_dig_data_interface/bank2_data_frm_matrix_set_DCO2 to AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1_6 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X32Y51.AQ Tcko 0.322 AD9249_dig_data_interface/bank2_data_frm_matrix_set_DCO2 AD9249_dig_data_interface/bank2_data_frm_matrix_set_DCO2 SLICE_X33Y51.A6 net (fanout=4) 0.400 AD9249_dig_data_interface/bank2_data_frm_matrix_set_DCO2 SLICE_X33Y51.A Tilo 0.061 AD9249_dig_data_interface/bank2_data_ack_vector_DCO2_reg<3> AD9249_dig_data_interface/_n0338_inv_SW0 SLICE_X33Y54.B1 net (fanout=1) 0.624 AD9249_dig_data_interface/N2 SLICE_X33Y54.B Tilo 0.061 AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_0<2> AD9249_dig_data_interface/_n0338_inv_rstpot SLICE_X9Y91.C2 net (fanout=96) 2.531 AD9249_dig_data_interface/_n0338_inv_rstpot SLICE_X9Y91.CLK Tas 0.060 AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1<7> AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1_6_dpot AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1_6 ------------------------------------------------- --------------------------- Total 4.059ns (0.504ns logic, 3.555ns route) (12.4% logic, 87.6% route) -------------------------------------------------------------------------------- Slack (setup path): 0.945ns (requirement - (data path - clock path skew + uncertainty)) Source: AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[2].ADC_channelXX_create_frame/Generate_frame/d_ack (FF) Destination: AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1_6 (FF) Requirement: 5.128ns Data Path Delay: 4.051ns (Levels of Logic = 3) Clock Path Skew: -0.097ns (1.326 - 1.423) Source Clock: AD9249_dig_data_interface/DCO_2_BUFG rising at 0.000ns Destination Clock: AD9249_dig_data_interface/DCO_2_BUFG rising at 5.128ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[2].ADC_channelXX_create_frame/Generate_frame/d_ack to AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1_6 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X33Y51.CQ Tcko 0.283 AD9249_dig_data_interface/bank2_data_ack_vector_DCO2_reg<3> AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[2].ADC_channelXX_create_frame/Generate_frame/d_ack SLICE_X33Y51.A1 net (fanout=2) 0.431 AD9249_dig_data_interface/bank2_data_ack_vector_DCO2_reg<2> SLICE_X33Y51.A Tilo 0.061 AD9249_dig_data_interface/bank2_data_ack_vector_DCO2_reg<3> AD9249_dig_data_interface/_n0338_inv_SW0 SLICE_X33Y54.B1 net (fanout=1) 0.624 AD9249_dig_data_interface/N2 SLICE_X33Y54.B Tilo 0.061 AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_0<2> AD9249_dig_data_interface/_n0338_inv_rstpot SLICE_X9Y91.C2 net (fanout=96) 2.531 AD9249_dig_data_interface/_n0338_inv_rstpot SLICE_X9Y91.CLK Tas 0.060 AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1<7> AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1_6_dpot AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1_6 ------------------------------------------------- --------------------------- Total 4.051ns (0.465ns logic, 3.586ns route) (11.5% logic, 88.5% route) -------------------------------------------------------------------------------- Slack (setup path): 0.967ns (requirement - (data path - clock path skew + uncertainty)) Source: AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[0].ADC_channelXX_create_frame/Generate_frame/d_ack (FF) Destination: AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1_6 (FF) Requirement: 5.128ns Data Path Delay: 4.029ns (Levels of Logic = 3) Clock Path Skew: -0.097ns (1.326 - 1.423) Source Clock: AD9249_dig_data_interface/DCO_2_BUFG rising at 0.000ns Destination Clock: AD9249_dig_data_interface/DCO_2_BUFG rising at 5.128ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[0].ADC_channelXX_create_frame/Generate_frame/d_ack to AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1_6 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X33Y51.AQ Tcko 0.283 AD9249_dig_data_interface/bank2_data_ack_vector_DCO2_reg<3> AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[0].ADC_channelXX_create_frame/Generate_frame/d_ack SLICE_X33Y51.A3 net (fanout=2) 0.409 AD9249_dig_data_interface/bank2_data_ack_vector_DCO2_reg<0> SLICE_X33Y51.A Tilo 0.061 AD9249_dig_data_interface/bank2_data_ack_vector_DCO2_reg<3> AD9249_dig_data_interface/_n0338_inv_SW0 SLICE_X33Y54.B1 net (fanout=1) 0.624 AD9249_dig_data_interface/N2 SLICE_X33Y54.B Tilo 0.061 AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_0<2> AD9249_dig_data_interface/_n0338_inv_rstpot SLICE_X9Y91.C2 net (fanout=96) 2.531 AD9249_dig_data_interface/_n0338_inv_rstpot SLICE_X9Y91.CLK Tas 0.060 AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1<7> AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1_6_dpot AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1_6 ------------------------------------------------- --------------------------- Total 4.029ns (0.465ns logic, 3.564ns route) (11.5% logic, 88.5% route) -------------------------------------------------------------------------------- Paths for end point AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1_7 (SLICE_X9Y91.D1), 9 paths -------------------------------------------------------------------------------- Slack (setup path): 0.944ns (requirement - (data path - clock path skew + uncertainty)) Source: AD9249_dig_data_interface/bank2_data_frm_matrix_set_DCO2 (FF) Destination: AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1_7 (FF) Requirement: 5.128ns Data Path Delay: 4.052ns (Levels of Logic = 3) Clock Path Skew: -0.097ns (1.326 - 1.423) Source Clock: AD9249_dig_data_interface/DCO_2_BUFG rising at 0.000ns Destination Clock: AD9249_dig_data_interface/DCO_2_BUFG rising at 5.128ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: AD9249_dig_data_interface/bank2_data_frm_matrix_set_DCO2 to AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1_7 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X32Y51.AQ Tcko 0.322 AD9249_dig_data_interface/bank2_data_frm_matrix_set_DCO2 AD9249_dig_data_interface/bank2_data_frm_matrix_set_DCO2 SLICE_X33Y51.A6 net (fanout=4) 0.400 AD9249_dig_data_interface/bank2_data_frm_matrix_set_DCO2 SLICE_X33Y51.A Tilo 0.061 AD9249_dig_data_interface/bank2_data_ack_vector_DCO2_reg<3> AD9249_dig_data_interface/_n0338_inv_SW0 SLICE_X33Y54.B1 net (fanout=1) 0.624 AD9249_dig_data_interface/N2 SLICE_X33Y54.B Tilo 0.061 AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_0<2> AD9249_dig_data_interface/_n0338_inv_rstpot SLICE_X9Y91.D1 net (fanout=96) 2.527 AD9249_dig_data_interface/_n0338_inv_rstpot SLICE_X9Y91.CLK Tas 0.057 AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1<7> AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1_7_dpot AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1_7 ------------------------------------------------- --------------------------- Total 4.052ns (0.501ns logic, 3.551ns route) (12.4% logic, 87.6% route) -------------------------------------------------------------------------------- Slack (setup path): 0.952ns (requirement - (data path - clock path skew + uncertainty)) Source: AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[2].ADC_channelXX_create_frame/Generate_frame/d_ack (FF) Destination: AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1_7 (FF) Requirement: 5.128ns Data Path Delay: 4.044ns (Levels of Logic = 3) Clock Path Skew: -0.097ns (1.326 - 1.423) Source Clock: AD9249_dig_data_interface/DCO_2_BUFG rising at 0.000ns Destination Clock: AD9249_dig_data_interface/DCO_2_BUFG rising at 5.128ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[2].ADC_channelXX_create_frame/Generate_frame/d_ack to AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1_7 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X33Y51.CQ Tcko 0.283 AD9249_dig_data_interface/bank2_data_ack_vector_DCO2_reg<3> AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[2].ADC_channelXX_create_frame/Generate_frame/d_ack SLICE_X33Y51.A1 net (fanout=2) 0.431 AD9249_dig_data_interface/bank2_data_ack_vector_DCO2_reg<2> SLICE_X33Y51.A Tilo 0.061 AD9249_dig_data_interface/bank2_data_ack_vector_DCO2_reg<3> AD9249_dig_data_interface/_n0338_inv_SW0 SLICE_X33Y54.B1 net (fanout=1) 0.624 AD9249_dig_data_interface/N2 SLICE_X33Y54.B Tilo 0.061 AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_0<2> AD9249_dig_data_interface/_n0338_inv_rstpot SLICE_X9Y91.D1 net (fanout=96) 2.527 AD9249_dig_data_interface/_n0338_inv_rstpot SLICE_X9Y91.CLK Tas 0.057 AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1<7> AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1_7_dpot AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1_7 ------------------------------------------------- --------------------------- Total 4.044ns (0.462ns logic, 3.582ns route) (11.4% logic, 88.6% route) -------------------------------------------------------------------------------- Slack (setup path): 0.974ns (requirement - (data path - clock path skew + uncertainty)) Source: AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[0].ADC_channelXX_create_frame/Generate_frame/d_ack (FF) Destination: AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1_7 (FF) Requirement: 5.128ns Data Path Delay: 4.022ns (Levels of Logic = 3) Clock Path Skew: -0.097ns (1.326 - 1.423) Source Clock: AD9249_dig_data_interface/DCO_2_BUFG rising at 0.000ns Destination Clock: AD9249_dig_data_interface/DCO_2_BUFG rising at 5.128ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[0].ADC_channelXX_create_frame/Generate_frame/d_ack to AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1_7 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X33Y51.AQ Tcko 0.283 AD9249_dig_data_interface/bank2_data_ack_vector_DCO2_reg<3> AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[0].ADC_channelXX_create_frame/Generate_frame/d_ack SLICE_X33Y51.A3 net (fanout=2) 0.409 AD9249_dig_data_interface/bank2_data_ack_vector_DCO2_reg<0> SLICE_X33Y51.A Tilo 0.061 AD9249_dig_data_interface/bank2_data_ack_vector_DCO2_reg<3> AD9249_dig_data_interface/_n0338_inv_SW0 SLICE_X33Y54.B1 net (fanout=1) 0.624 AD9249_dig_data_interface/N2 SLICE_X33Y54.B Tilo 0.061 AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_0<2> AD9249_dig_data_interface/_n0338_inv_rstpot SLICE_X9Y91.D1 net (fanout=96) 2.527 AD9249_dig_data_interface/_n0338_inv_rstpot SLICE_X9Y91.CLK Tas 0.057 AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1<7> AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1_7_dpot AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1_7 ------------------------------------------------- --------------------------- Total 4.022ns (0.462ns logic, 3.560ns route) (11.5% logic, 88.5% route) -------------------------------------------------------------------------------- Paths for end point AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1_4 (SLICE_X9Y91.A3), 9 paths -------------------------------------------------------------------------------- Slack (setup path): 1.051ns (requirement - (data path - clock path skew + uncertainty)) Source: AD9249_dig_data_interface/bank2_data_frm_matrix_set_DCO2 (FF) Destination: AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1_4 (FF) Requirement: 5.128ns Data Path Delay: 3.945ns (Levels of Logic = 3) Clock Path Skew: -0.097ns (1.326 - 1.423) Source Clock: AD9249_dig_data_interface/DCO_2_BUFG rising at 0.000ns Destination Clock: AD9249_dig_data_interface/DCO_2_BUFG rising at 5.128ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: AD9249_dig_data_interface/bank2_data_frm_matrix_set_DCO2 to AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1_4 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X32Y51.AQ Tcko 0.322 AD9249_dig_data_interface/bank2_data_frm_matrix_set_DCO2 AD9249_dig_data_interface/bank2_data_frm_matrix_set_DCO2 SLICE_X33Y51.A6 net (fanout=4) 0.400 AD9249_dig_data_interface/bank2_data_frm_matrix_set_DCO2 SLICE_X33Y51.A Tilo 0.061 AD9249_dig_data_interface/bank2_data_ack_vector_DCO2_reg<3> AD9249_dig_data_interface/_n0338_inv_SW0 SLICE_X33Y54.B1 net (fanout=1) 0.624 AD9249_dig_data_interface/N2 SLICE_X33Y54.B Tilo 0.061 AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_0<2> AD9249_dig_data_interface/_n0338_inv_rstpot SLICE_X9Y91.A3 net (fanout=96) 2.417 AD9249_dig_data_interface/_n0338_inv_rstpot SLICE_X9Y91.CLK Tas 0.060 AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1<7> AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1_4_dpot AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1_4 ------------------------------------------------- --------------------------- Total 3.945ns (0.504ns logic, 3.441ns route) (12.8% logic, 87.2% route) -------------------------------------------------------------------------------- Slack (setup path): 1.059ns (requirement - (data path - clock path skew + uncertainty)) Source: AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[2].ADC_channelXX_create_frame/Generate_frame/d_ack (FF) Destination: AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1_4 (FF) Requirement: 5.128ns Data Path Delay: 3.937ns (Levels of Logic = 3) Clock Path Skew: -0.097ns (1.326 - 1.423) Source Clock: AD9249_dig_data_interface/DCO_2_BUFG rising at 0.000ns Destination Clock: AD9249_dig_data_interface/DCO_2_BUFG rising at 5.128ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[2].ADC_channelXX_create_frame/Generate_frame/d_ack to AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1_4 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X33Y51.CQ Tcko 0.283 AD9249_dig_data_interface/bank2_data_ack_vector_DCO2_reg<3> AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[2].ADC_channelXX_create_frame/Generate_frame/d_ack SLICE_X33Y51.A1 net (fanout=2) 0.431 AD9249_dig_data_interface/bank2_data_ack_vector_DCO2_reg<2> SLICE_X33Y51.A Tilo 0.061 AD9249_dig_data_interface/bank2_data_ack_vector_DCO2_reg<3> AD9249_dig_data_interface/_n0338_inv_SW0 SLICE_X33Y54.B1 net (fanout=1) 0.624 AD9249_dig_data_interface/N2 SLICE_X33Y54.B Tilo 0.061 AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_0<2> AD9249_dig_data_interface/_n0338_inv_rstpot SLICE_X9Y91.A3 net (fanout=96) 2.417 AD9249_dig_data_interface/_n0338_inv_rstpot SLICE_X9Y91.CLK Tas 0.060 AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1<7> AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1_4_dpot AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1_4 ------------------------------------------------- --------------------------- Total 3.937ns (0.465ns logic, 3.472ns route) (11.8% logic, 88.2% route) -------------------------------------------------------------------------------- Slack (setup path): 1.081ns (requirement - (data path - clock path skew + uncertainty)) Source: AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[0].ADC_channelXX_create_frame/Generate_frame/d_ack (FF) Destination: AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1_4 (FF) Requirement: 5.128ns Data Path Delay: 3.915ns (Levels of Logic = 3) Clock Path Skew: -0.097ns (1.326 - 1.423) Source Clock: AD9249_dig_data_interface/DCO_2_BUFG rising at 0.000ns Destination Clock: AD9249_dig_data_interface/DCO_2_BUFG rising at 5.128ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[0].ADC_channelXX_create_frame/Generate_frame/d_ack to AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1_4 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X33Y51.AQ Tcko 0.283 AD9249_dig_data_interface/bank2_data_ack_vector_DCO2_reg<3> AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[0].ADC_channelXX_create_frame/Generate_frame/d_ack SLICE_X33Y51.A3 net (fanout=2) 0.409 AD9249_dig_data_interface/bank2_data_ack_vector_DCO2_reg<0> SLICE_X33Y51.A Tilo 0.061 AD9249_dig_data_interface/bank2_data_ack_vector_DCO2_reg<3> AD9249_dig_data_interface/_n0338_inv_SW0 SLICE_X33Y54.B1 net (fanout=1) 0.624 AD9249_dig_data_interface/N2 SLICE_X33Y54.B Tilo 0.061 AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_0<2> AD9249_dig_data_interface/_n0338_inv_rstpot SLICE_X9Y91.A3 net (fanout=96) 2.417 AD9249_dig_data_interface/_n0338_inv_rstpot SLICE_X9Y91.CLK Tas 0.060 AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1<7> AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1_4_dpot AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_1_4 ------------------------------------------------- --------------------------- Total 3.915ns (0.465ns logic, 3.450ns route) (11.9% logic, 88.1% route) -------------------------------------------------------------------------------- Hold Paths: TS_DCO2_n = PERIOD TIMEGRP "DCO2_n" 195 MHz HIGH 50%; -------------------------------------------------------------------------------- Paths for end point AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_5_4 (SLICE_X36Y39.A5), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.065ns (requirement - (clock path skew + uncertainty - data path)) Source: AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[5].ADC_channelXX_create_frame/Generate_frame/d_frm_out_reg_4 (FF) Destination: AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_5_4 (FF) Requirement: 0.000ns Data Path Delay: 0.153ns (Levels of Logic = 1) Clock Path Skew: 0.088ns (0.679 - 0.591) Source Clock: AD9249_dig_data_interface/DCO_2_BUFG rising at 5.128ns Destination Clock: AD9249_dig_data_interface/DCO_2_BUFG rising at 5.128ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[5].ADC_channelXX_create_frame/Generate_frame/d_frm_out_reg_4 to AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_5_4 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X36Y41.AQ Tcko 0.115 AD9249_dig_data_interface/bank2_data_frm_matrix_DCO2_reg<5><7> AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[5].ADC_channelXX_create_frame/Generate_frame/d_frm_out_reg_4 SLICE_X36Y39.A5 net (fanout=1) 0.114 AD9249_dig_data_interface/bank2_data_frm_matrix_DCO2_reg<5><4> SLICE_X36Y39.CLK Tah (-Th) 0.076 AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_5<7> AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_5_4_dpot AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_5_4 ------------------------------------------------- --------------------------- Total 0.153ns (0.039ns logic, 0.114ns route) (25.5% logic, 74.5% route) -------------------------------------------------------------------------------- Paths for end point AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_5_6 (SLICE_X36Y39.C5), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.065ns (requirement - (clock path skew + uncertainty - data path)) Source: AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[5].ADC_channelXX_create_frame/Generate_frame/d_frm_out_reg_6 (FF) Destination: AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_5_6 (FF) Requirement: 0.000ns Data Path Delay: 0.153ns (Levels of Logic = 1) Clock Path Skew: 0.088ns (0.679 - 0.591) Source Clock: AD9249_dig_data_interface/DCO_2_BUFG rising at 5.128ns Destination Clock: AD9249_dig_data_interface/DCO_2_BUFG rising at 5.128ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[5].ADC_channelXX_create_frame/Generate_frame/d_frm_out_reg_6 to AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_5_6 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X36Y41.CQ Tcko 0.115 AD9249_dig_data_interface/bank2_data_frm_matrix_DCO2_reg<5><7> AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[5].ADC_channelXX_create_frame/Generate_frame/d_frm_out_reg_6 SLICE_X36Y39.C5 net (fanout=1) 0.114 AD9249_dig_data_interface/bank2_data_frm_matrix_DCO2_reg<5><6> SLICE_X36Y39.CLK Tah (-Th) 0.076 AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_5<7> AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_5_6_dpot AD9249_dig_data_interface/bank2_data_frm_matrix_transfer_reg_5_6 ------------------------------------------------- --------------------------- Total 0.153ns (0.039ns logic, 0.114ns route) (25.5% logic, 74.5% route) -------------------------------------------------------------------------------- Paths for end point AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[4].ADC_channelXX_create_frame/Generate_frame/data_in_frm_pipe_12 (SLICE_X35Y39.AX), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.075ns (requirement - (clock path skew + uncertainty - data path)) Source: AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[4].ADC_channelXX_create_frame/Generate_frame/data_in_frm_pipe_10 (FF) Destination: AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[4].ADC_channelXX_create_frame/Generate_frame/data_in_frm_pipe_12 (FF) Requirement: 0.000ns Data Path Delay: 0.164ns (Levels of Logic = 0) Clock Path Skew: 0.089ns (0.669 - 0.580) Source Clock: AD9249_dig_data_interface/DCO_2_BUFG rising at 5.128ns Destination Clock: AD9249_dig_data_interface/DCO_2_BUFG rising at 5.128ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[4].ADC_channelXX_create_frame/Generate_frame/data_in_frm_pipe_10 to AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[4].ADC_channelXX_create_frame/Generate_frame/data_in_frm_pipe_12 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X35Y40.CQ Tcko 0.098 AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[4].ADC_channelXX_create_frame/ch_pipe<11> AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[4].ADC_channelXX_create_frame/Generate_frame/data_in_frm_pipe_10 SLICE_X35Y39.AX net (fanout=2) 0.142 AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[4].ADC_channelXX_create_frame/ch_pipe<10> SLICE_X35Y39.CLK Tckdi (-Th) 0.076 AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[4].ADC_channelXX_create_frame/ch_pipe<13> AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[4].ADC_channelXX_create_frame/Generate_frame/data_in_frm_pipe_12 ------------------------------------------------- --------------------------- Total 0.164ns (0.022ns logic, 0.142ns route) (13.4% logic, 86.6% route) -------------------------------------------------------------------------------- Component Switching Limit Checks: TS_DCO2_n = PERIOD TIMEGRP "DCO2_n" 195 MHz HIGH 50%; -------------------------------------------------------------------------------- Slack: 3.795ns (period - min period limit) Period: 5.128ns Min period limit: 1.333ns (750.188MHz) (Tbcper_I) Physical resource: AD9249_dig_data_interface/DCO_2_BUFG/I0 Logical resource: AD9249_dig_data_interface/DCO_2_BUFG/I0 Location pin: BUFGCTRL_X0Y31.I0 Clock network: AD9249_dig_data_interface/DCO_2 -------------------------------------------------------------------------------- Slack: 3.814ns (period - min period limit) Period: 5.128ns Min period limit: 1.314ns (761.035MHz) (Tickper) Physical resource: AD9249_dig_data_interface/ADC_bank2/fco_data_nib<1>/CLK Logical resource: AD9249_dig_data_interface/ADC_bank2/FCO_DDR/iddr_inst/CK Location pin: ILOGIC_X2Y95.CLK Clock network: AD9249_dig_data_interface/DCO_2_BUFG -------------------------------------------------------------------------------- Slack: 3.814ns (period - min period limit) Period: 5.128ns Min period limit: 1.314ns (761.035MHz) (Tickper) Physical resource: AD9249_dig_data_interface/ADC_bank2/fco_data_nib<1>/CLKB Logical resource: AD9249_dig_data_interface/ADC_bank2/FCO_DDR/iddr_inst/CKB Location pin: ILOGIC_X2Y95.CLKB Clock network: AD9249_dig_data_interface/DCO_2_BUFG -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_FCO1_p = PERIOD TIMEGRP "FCO1_p" 32.5 MHz HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 component switching limit errors) Minimum period is 1.314ns. -------------------------------------------------------------------------------- Component Switching Limit Checks: TS_FCO1_p = PERIOD TIMEGRP "FCO1_p" 32.5 MHz HIGH 50%; -------------------------------------------------------------------------------- Slack: 29.455ns (period - min period limit) Period: 30.769ns Min period limit: 1.314ns (761.035MHz) (Tickper) Physical resource: AD9249_dig_data_interface/ADC_bank1/fco_data_nib<1>/CLK Logical resource: AD9249_dig_data_interface/ADC_bank1/FCO_DDR/iddr_inst/CK Location pin: ILOGIC_X2Y117.CLK Clock network: AD9249_dig_data_interface/DCO_1_BUFG -------------------------------------------------------------------------------- Slack: 29.455ns (period - min period limit) Period: 30.769ns Min period limit: 1.314ns (761.035MHz) (Tickper) Physical resource: AD9249_dig_data_interface/ADC_bank1/fco_data_nib<1>/CLKB Logical resource: AD9249_dig_data_interface/ADC_bank1/FCO_DDR/iddr_inst/CKB Location pin: ILOGIC_X2Y117.CLKB Clock network: AD9249_dig_data_interface/DCO_1_BUFG -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_FCO2_p = PERIOD TIMEGRP "FCO2_p" 32.5 MHz HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 component switching limit errors) Minimum period is 1.314ns. -------------------------------------------------------------------------------- Component Switching Limit Checks: TS_FCO2_p = PERIOD TIMEGRP "FCO2_p" 32.5 MHz HIGH 50%; -------------------------------------------------------------------------------- Slack: 29.455ns (period - min period limit) Period: 30.769ns Min period limit: 1.314ns (761.035MHz) (Tickper) Physical resource: AD9249_dig_data_interface/ADC_bank2/fco_data_nib<1>/CLK Logical resource: AD9249_dig_data_interface/ADC_bank2/FCO_DDR/iddr_inst/CK Location pin: ILOGIC_X2Y95.CLK Clock network: AD9249_dig_data_interface/DCO_2_BUFG -------------------------------------------------------------------------------- Slack: 29.455ns (period - min period limit) Period: 30.769ns Min period limit: 1.314ns (761.035MHz) (Tickper) Physical resource: AD9249_dig_data_interface/ADC_bank2/fco_data_nib<1>/CLKB Logical resource: AD9249_dig_data_interface/ADC_bank2/FCO_DDR/iddr_inst/CKB Location pin: ILOGIC_X2Y95.CLKB Clock network: AD9249_dig_data_interface/DCO_2_BUFG -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_System_clk_management_spi_2x_sclk = PERIOD TIMEGRP "System_clk_management_spi_2x_sclk" TS_evb_ref_clk_p * 0.1 PHASE -45 ns LOW 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 615 paths analyzed, 369 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) Minimum period is 30.200ns. -------------------------------------------------------------------------------- Paths for end point AD9249_spi_interface/Instruction_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_0 (SLICE_X38Y32.AX), 1 path -------------------------------------------------------------------------------- Slack (setup path): 6.980ns (requirement - (data path - clock path skew + uncertainty)) Source: AD9249_spi_interface/Instruction_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_0 (FF) Destination: AD9249_spi_interface/Instruction_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_0 (FF) Requirement: 10.000ns Data Path Delay: 2.526ns (Levels of Logic = 0) Clock Path Skew: -0.233ns (2.127 - 2.360) Source Clock: debug_h1_20_OBUF rising at 95.000ns Destination Clock: spi_2x_sclk rising at 105.000ns Clock Uncertainty: 0.261ns Clock Uncertainty: 0.261ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.272ns Phase Error (PE): 0.120ns Maximum Data Path at Slow Process Corner: AD9249_spi_interface/Instruction_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_0 to AD9249_spi_interface/Instruction_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_0 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X38Y31.AMUX Tshcko 0.357 AD9249_spi_interface/Instruction_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<4> AD9249_spi_interface/Instruction_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_0 SLICE_X38Y32.AX net (fanout=1) 2.153 AD9249_spi_interface/Instruction_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<0> SLICE_X38Y32.CLK Tdick 0.016 AD9249_spi_interface/Instruction_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<3> AD9249_spi_interface/Instruction_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_0 ------------------------------------------------- --------------------------- Total 2.526ns (0.373ns logic, 2.153ns route) (14.8% logic, 85.2% route) -------------------------------------------------------------------------------- Paths for end point AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_1 (SLICE_X35Y36.BX), 1 path -------------------------------------------------------------------------------- Slack (setup path): 7.374ns (requirement - (data path - clock path skew + uncertainty)) Source: AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_1 (FF) Destination: AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_1 (FF) Requirement: 10.000ns Data Path Delay: 2.136ns (Levels of Logic = 0) Clock Path Skew: -0.229ns (2.112 - 2.341) Source Clock: debug_h1_20_OBUF rising at 95.000ns Destination Clock: spi_2x_sclk rising at 105.000ns Clock Uncertainty: 0.261ns Clock Uncertainty: 0.261ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.272ns Phase Error (PE): 0.120ns Maximum Data Path at Slow Process Corner: AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_1 to AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_1 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X33Y36.AQ Tcko 0.283 AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<4> AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_1 SLICE_X35Y36.BX net (fanout=1) 1.837 AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/D<1> SLICE_X35Y36.CLK Tdick 0.016 AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[2].rd_stg_inst/D<3> AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].rd_stg_inst/Q_reg_1 ------------------------------------------------- --------------------------- Total 2.136ns (0.299ns logic, 1.837ns route) (14.0% logic, 86.0% route) -------------------------------------------------------------------------------- Paths for end point AD9249_spi_interface/cur_state_FSM_FFd2 (SLICE_X34Y31.A5), 7 paths -------------------------------------------------------------------------------- Slack (setup path): 7.650ns (requirement - (data path - clock path skew + uncertainty)) Source: AD9249_spi_interface/gen_chipscope.VIO_SPI/U0/I_VIO/GEN_SYNC_OUT[1].SYNC_OUT_CELL/USER_REG (FF) Destination: AD9249_spi_interface/cur_state_FSM_FFd2 (FF) Requirement: 10.000ns Data Path Delay: 1.867ns (Levels of Logic = 2) Clock Path Skew: -0.222ns (2.110 - 2.332) Source Clock: debug_h1_20_OBUF rising at 95.000ns Destination Clock: spi_2x_sclk rising at 105.000ns Clock Uncertainty: 0.261ns Clock Uncertainty: 0.261ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.272ns Phase Error (PE): 0.120ns Maximum Data Path at Slow Process Corner: AD9249_spi_interface/gen_chipscope.VIO_SPI/U0/I_VIO/GEN_SYNC_OUT[1].SYNC_OUT_CELL/USER_REG to AD9249_spi_interface/cur_state_FSM_FFd2 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X30Y37.AQ Tcko 0.322 AD9249_spi_interface/vio_out<1> AD9249_spi_interface/gen_chipscope.VIO_SPI/U0/I_VIO/GEN_SYNC_OUT[1].SYNC_OUT_CELL/USER_REG SLICE_X34Y31.B2 net (fanout=11) 1.039 AD9249_spi_interface/vio_out<1> SLICE_X34Y31.BMUX Tilo 0.175 AD9249_spi_interface/cur_state_FSM_FFd3 AD9249_spi_interface/cur_state_FSM_FFd2-In1 SLICE_X34Y31.A5 net (fanout=1) 0.271 AD9249_spi_interface/cur_state_FSM_FFd2-In1 SLICE_X34Y31.CLK Tas 0.060 AD9249_spi_interface/cur_state_FSM_FFd3 AD9249_spi_interface/cur_state_FSM_FFd2-In3 AD9249_spi_interface/cur_state_FSM_FFd2 ------------------------------------------------- --------------------------- Total 1.867ns (0.557ns logic, 1.310ns route) (29.8% logic, 70.2% route) -------------------------------------------------------------------------------- Slack (setup path): 7.679ns (requirement - (data path - clock path skew + uncertainty)) Source: cur_state_FSM_FFd1 (FF) Destination: AD9249_spi_interface/cur_state_FSM_FFd2 (FF) Requirement: 10.000ns Data Path Delay: 1.833ns (Levels of Logic = 3) Clock Path Skew: -0.227ns (2.110 - 2.337) Source Clock: debug_h1_20_OBUF rising at 95.000ns Destination Clock: spi_2x_sclk rising at 105.000ns Clock Uncertainty: 0.261ns Clock Uncertainty: 0.261ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.272ns Phase Error (PE): 0.120ns Maximum Data Path at Slow Process Corner: cur_state_FSM_FFd1 to AD9249_spi_interface/cur_state_FSM_FFd2 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X33Y30.AQ Tcko 0.283 cur_state_FSM_FFd3 cur_state_FSM_FFd1 SLICE_X33Y31.A4 net (fanout=11) 0.462 cur_state_FSM_FFd1 SLICE_X33Y31.A Tilo 0.061 AD9249_spi_interface/vio_out<13> Mmux_spi_instr_bytes21 SLICE_X34Y31.B3 net (fanout=1) 0.527 spi_instr_bytes<15> SLICE_X34Y31.BMUX Tilo 0.169 AD9249_spi_interface/cur_state_FSM_FFd3 AD9249_spi_interface/cur_state_FSM_FFd2-In1 SLICE_X34Y31.A5 net (fanout=1) 0.271 AD9249_spi_interface/cur_state_FSM_FFd2-In1 SLICE_X34Y31.CLK Tas 0.060 AD9249_spi_interface/cur_state_FSM_FFd3 AD9249_spi_interface/cur_state_FSM_FFd2-In3 AD9249_spi_interface/cur_state_FSM_FFd2 ------------------------------------------------- --------------------------- Total 1.833ns (0.573ns logic, 1.260ns route) (31.3% logic, 68.7% route) -------------------------------------------------------------------------------- Slack (setup path): 7.705ns (requirement - (data path - clock path skew + uncertainty)) Source: cur_state_FSM_FFd3 (FF) Destination: AD9249_spi_interface/cur_state_FSM_FFd2 (FF) Requirement: 10.000ns Data Path Delay: 1.807ns (Levels of Logic = 3) Clock Path Skew: -0.227ns (2.110 - 2.337) Source Clock: debug_h1_20_OBUF rising at 95.000ns Destination Clock: spi_2x_sclk rising at 105.000ns Clock Uncertainty: 0.261ns Clock Uncertainty: 0.261ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.272ns Phase Error (PE): 0.120ns Maximum Data Path at Slow Process Corner: cur_state_FSM_FFd3 to AD9249_spi_interface/cur_state_FSM_FFd2 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X33Y30.CQ Tcko 0.283 cur_state_FSM_FFd3 cur_state_FSM_FFd3 SLICE_X33Y31.A3 net (fanout=12) 0.436 cur_state_FSM_FFd3 SLICE_X33Y31.A Tilo 0.061 AD9249_spi_interface/vio_out<13> Mmux_spi_instr_bytes21 SLICE_X34Y31.B3 net (fanout=1) 0.527 spi_instr_bytes<15> SLICE_X34Y31.BMUX Tilo 0.169 AD9249_spi_interface/cur_state_FSM_FFd3 AD9249_spi_interface/cur_state_FSM_FFd2-In1 SLICE_X34Y31.A5 net (fanout=1) 0.271 AD9249_spi_interface/cur_state_FSM_FFd2-In1 SLICE_X34Y31.CLK Tas 0.060 AD9249_spi_interface/cur_state_FSM_FFd3 AD9249_spi_interface/cur_state_FSM_FFd2-In3 AD9249_spi_interface/cur_state_FSM_FFd2 ------------------------------------------------- --------------------------- Total 1.807ns (0.573ns logic, 1.234ns route) (31.7% logic, 68.3% route) -------------------------------------------------------------------------------- Hold Paths: TS_System_clk_management_spi_2x_sclk = PERIOD TIMEGRP "System_clk_management_spi_2x_sclk" TS_evb_ref_clk_p * 0.1 PHASE -45 ns LOW 50%; -------------------------------------------------------------------------------- Paths for end point AD9249_spi_interface/cur_state_FSM_FFd2 (SLICE_X34Y31.A5), 7 paths -------------------------------------------------------------------------------- Slack (hold path): 0.034ns (requirement - (clock path skew + uncertainty - data path)) Source: AD9249_spi_interface/gen_chipscope.VIO_SPI/U0/I_VIO/GEN_SYNC_OUT[17].SYNC_OUT_CELL/USER_REG (FF) Destination: AD9249_spi_interface/cur_state_FSM_FFd2 (FF) Requirement: 0.000ns Data Path Delay: 0.444ns (Levels of Logic = 2) Clock Path Skew: 0.149ns (1.119 - 0.970) Source Clock: debug_h1_20_OBUF rising at 105.000ns Destination Clock: spi_2x_sclk rising at 105.000ns Clock Uncertainty: 0.261ns Clock Uncertainty: 0.261ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.272ns Phase Error (PE): 0.120ns Minimum Data Path at Fast Process Corner: AD9249_spi_interface/gen_chipscope.VIO_SPI/U0/I_VIO/GEN_SYNC_OUT[17].SYNC_OUT_CELL/USER_REG to AD9249_spi_interface/cur_state_FSM_FFd2 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X34Y30.AQ Tcko 0.098 AD9249_spi_interface/vio_out<17> AD9249_spi_interface/gen_chipscope.VIO_SPI/U0/I_VIO/GEN_SYNC_OUT[17].SYNC_OUT_CELL/USER_REG SLICE_X34Y31.B1 net (fanout=1) 0.204 AD9249_spi_interface/vio_out<17> SLICE_X34Y31.BMUX Tilo 0.075 AD9249_spi_interface/cur_state_FSM_FFd3 AD9249_spi_interface/cur_state_FSM_FFd2-In1 SLICE_X34Y31.A5 net (fanout=1) 0.122 AD9249_spi_interface/cur_state_FSM_FFd2-In1 SLICE_X34Y31.CLK Tah (-Th) 0.055 AD9249_spi_interface/cur_state_FSM_FFd3 AD9249_spi_interface/cur_state_FSM_FFd2-In3 AD9249_spi_interface/cur_state_FSM_FFd2 ------------------------------------------------- --------------------------- Total 0.444ns (0.118ns logic, 0.326ns route) (26.6% logic, 73.4% route) -------------------------------------------------------------------------------- Slack (hold path): 0.217ns (requirement - (clock path skew + uncertainty - data path)) Source: cur_state_FSM_FFd2 (FF) Destination: AD9249_spi_interface/cur_state_FSM_FFd2 (FF) Requirement: 0.000ns Data Path Delay: 0.629ns (Levels of Logic = 3) Clock Path Skew: 0.151ns (1.119 - 0.968) Source Clock: debug_h1_20_OBUF rising at 105.000ns Destination Clock: spi_2x_sclk rising at 105.000ns Clock Uncertainty: 0.261ns Clock Uncertainty: 0.261ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.272ns Phase Error (PE): 0.120ns Minimum Data Path at Fast Process Corner: cur_state_FSM_FFd2 to AD9249_spi_interface/cur_state_FSM_FFd2 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X33Y30.BQ Tcko 0.098 cur_state_FSM_FFd3 cur_state_FSM_FFd2 SLICE_X33Y31.A5 net (fanout=12) 0.135 cur_state_FSM_FFd2 SLICE_X33Y31.A Tilo 0.034 AD9249_spi_interface/vio_out<13> Mmux_spi_instr_bytes21 SLICE_X34Y31.B3 net (fanout=1) 0.216 spi_instr_bytes<15> SLICE_X34Y31.BMUX Tilo 0.079 AD9249_spi_interface/cur_state_FSM_FFd3 AD9249_spi_interface/cur_state_FSM_FFd2-In1 SLICE_X34Y31.A5 net (fanout=1) 0.122 AD9249_spi_interface/cur_state_FSM_FFd2-In1 SLICE_X34Y31.CLK Tah (-Th) 0.055 AD9249_spi_interface/cur_state_FSM_FFd3 AD9249_spi_interface/cur_state_FSM_FFd2-In3 AD9249_spi_interface/cur_state_FSM_FFd2 ------------------------------------------------- --------------------------- Total 0.629ns (0.156ns logic, 0.473ns route) (24.8% logic, 75.2% route) -------------------------------------------------------------------------------- Slack (hold path): 0.245ns (requirement - (clock path skew + uncertainty - data path)) Source: AD9249_spi_interface/gen_chipscope.VIO_SPI/U0/I_VIO/GEN_SYNC_OUT[0].SYNC_OUT_CELL/USER_REG (FF) Destination: AD9249_spi_interface/cur_state_FSM_FFd2 (FF) Requirement: 0.000ns Data Path Delay: 0.663ns (Levels of Logic = 2) Clock Path Skew: 0.157ns (1.119 - 0.962) Source Clock: debug_h1_20_OBUF rising at 105.000ns Destination Clock: spi_2x_sclk rising at 105.000ns Clock Uncertainty: 0.261ns Clock Uncertainty: 0.261ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.272ns Phase Error (PE): 0.120ns Minimum Data Path at Fast Process Corner: AD9249_spi_interface/gen_chipscope.VIO_SPI/U0/I_VIO/GEN_SYNC_OUT[0].SYNC_OUT_CELL/USER_REG to AD9249_spi_interface/cur_state_FSM_FFd2 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X28Y38.AQ Tcko 0.115 AD9249_spi_interface/vio_out<0> AD9249_spi_interface/gen_chipscope.VIO_SPI/U0/I_VIO/GEN_SYNC_OUT[0].SYNC_OUT_CELL/USER_REG SLICE_X34Y31.B4 net (fanout=19) 0.402 AD9249_spi_interface/vio_out<0> SLICE_X34Y31.BMUX Tilo 0.079 AD9249_spi_interface/cur_state_FSM_FFd3 AD9249_spi_interface/cur_state_FSM_FFd2-In1 SLICE_X34Y31.A5 net (fanout=1) 0.122 AD9249_spi_interface/cur_state_FSM_FFd2-In1 SLICE_X34Y31.CLK Tah (-Th) 0.055 AD9249_spi_interface/cur_state_FSM_FFd3 AD9249_spi_interface/cur_state_FSM_FFd2-In3 AD9249_spi_interface/cur_state_FSM_FFd2 ------------------------------------------------- --------------------------- Total 0.663ns (0.139ns logic, 0.524ns route) (21.0% logic, 79.0% route) -------------------------------------------------------------------------------- Paths for end point AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4 (SLICE_X34Y36.CX), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.118ns (requirement - (clock path skew + uncertainty - data path)) Source: AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4 (FF) Destination: AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4 (FF) Requirement: 0.000ns Data Path Delay: 0.131ns (Levels of Logic = 0) Clock Path Skew: 0.013ns (0.066 - 0.053) Source Clock: spi_2x_sclk rising at 105.000ns Destination Clock: spi_2x_sclk rising at 105.000ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4 to AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X35Y34.DQ Tcko 0.098 AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<4> AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_4 SLICE_X34Y36.CX net (fanout=4) 0.109 AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1<4> SLICE_X34Y36.CLK Tckdi (-Th) 0.076 AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[1].wr_stg_inst/D<4> AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_4 ------------------------------------------------- --------------------------- Total 0.131ns (0.022ns logic, 0.109ns route) (16.8% logic, 83.2% route) -------------------------------------------------------------------------------- Paths for end point AD9249_spi_interface/Instruction_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4 (SLICE_X36Y32.C4), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.123ns (requirement - (clock path skew + uncertainty - data path)) Source: AD9249_spi_interface/Instruction_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2 (FF) Destination: AD9249_spi_interface/Instruction_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4 (FF) Requirement: 0.000ns Data Path Delay: 0.123ns (Levels of Logic = 1) Clock Path Skew: 0.000ns Source Clock: spi_2x_sclk rising at 105.000ns Destination Clock: spi_2x_sclk rising at 105.000ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: AD9249_spi_interface/Instruction_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2 to AD9249_spi_interface/Instruction_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X36Y32.BQ Tcko 0.115 AD9249_spi_interface/Instruction_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<3> AD9249_spi_interface/Instruction_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_2 SLICE_X36Y32.C4 net (fanout=4) 0.109 AD9249_spi_interface/Instruction_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<2> SLICE_X36Y32.CLK Tah (-Th) 0.101 AD9249_spi_interface/Instruction_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count<3> AD9249_spi_interface/Instruction_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count[4]_GND_186_o_add_0_OUT<4>1 AD9249_spi_interface/Instruction_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_4 ------------------------------------------------- --------------------------- Total 0.123ns (0.014ns logic, 0.109ns route) (11.4% logic, 88.6% route) -------------------------------------------------------------------------------- Component Switching Limit Checks: TS_System_clk_management_spi_2x_sclk = PERIOD TIMEGRP "System_clk_management_spi_2x_sclk" TS_evb_ref_clk_p * 0.1 PHASE -45 ns LOW 50%; -------------------------------------------------------------------------------- Slack: 98.148ns (period - min period limit) Period: 100.000ns Min period limit: 1.852ns (539.957MHz) (Trper_CLKA) Physical resource: AD9249_spi_interface/Instruction_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram/CLKARDCLK Logical resource: AD9249_spi_interface/Instruction_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram/CLKARDCLK Location pin: RAMB18_X2Y5.CLKARDCLK Clock network: spi_2x_sclk -------------------------------------------------------------------------------- Slack: 98.148ns (period - min period limit) Period: 100.000ns Min period limit: 1.852ns (539.957MHz) (Trper_CLKA) Physical resource: AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram/CLKARDCLK Logical resource: AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram/CLKARDCLK Location pin: RAMB18_X1Y5.CLKARDCLK Clock network: spi_2x_sclk -------------------------------------------------------------------------------- Slack: 98.667ns (period - min period limit) Period: 100.000ns Min period limit: 1.333ns (750.188MHz) (Tbcper_I) Physical resource: System_clk_management/spi_2x_sclk_BUFG/I0 Logical resource: System_clk_management/spi_2x_sclk_BUFG/I0 Location pin: BUFGCTRL_X0Y1.I0 Clock network: System_clk_management/spi_2x_sclk -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_System_clk_management_sys_clk = PERIOD TIMEGRP "System_clk_management_sys_clk" TS_evb_ref_clk_p LOW 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 7983 paths analyzed, 5460 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) Minimum period is 4.685ns. -------------------------------------------------------------------------------- Paths for end point AD9249_spi_interface/gen_chipscope.LogicAnalyzer_SPI/U0/I_TQ0.G_TW[6].U_TQ (SLICE_X34Y28.C3), 13 paths -------------------------------------------------------------------------------- Slack (setup path): 5.315ns (requirement - (data path - clock path skew + uncertainty)) Source: AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram (RAM) Destination: AD9249_spi_interface/gen_chipscope.LogicAnalyzer_SPI/U0/I_TQ0.G_TW[6].U_TQ (FF) Requirement: 10.000ns Data Path Delay: 4.139ns (Levels of Logic = 2) Clock Path Skew: -0.285ns (2.107 - 2.392) Source Clock: spi_2x_sclk rising at 5.000ns Destination Clock: debug_h1_20_OBUF rising at 15.000ns Clock Uncertainty: 0.261ns Clock Uncertainty: 0.261ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.272ns Phase Error (PE): 0.120ns Maximum Data Path at Slow Process Corner: AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram to AD9249_spi_interface/gen_chipscope.LogicAnalyzer_SPI/U0/I_TQ0.G_TW[6].U_TQ Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- RAMB18_X1Y5.DOADO1 Trcko_DOA 1.784 AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram SLICE_X29Y18.D1 net (fanout=1) 1.120 AD9249_spi_interface/data_byte_out<1> SLICE_X29Y18.CMUX Topdc 0.304 AD9249_spi_interface/FPGA_master/data_cnt[2]_data_byte[7]_Mux_44_o AD9249_spi_interface/FPGA_master/Mmux_data_cnt[2]_data_byte[7]_Mux_44_o_4 AD9249_spi_interface/FPGA_master/Mmux_data_cnt[2]_data_byte[7]_Mux_44_o_2_f7 SLICE_X34Y28.C3 net (fanout=1) 0.871 AD9249_spi_interface/FPGA_master/data_cnt[2]_data_byte[7]_Mux_44_o SLICE_X34Y28.CLK Tas 0.060 AD9249_spi_interface/gen_chipscope.LogicAnalyzer_SPI/U0/iTRIG_IN<17> AD9249_spi_interface/FPGA_master/cur_state_sdo AD9249_spi_interface/gen_chipscope.LogicAnalyzer_SPI/U0/I_TQ0.G_TW[6].U_TQ ------------------------------------------------- --------------------------- Total 4.139ns (2.148ns logic, 1.991ns route) (51.9% logic, 48.1% route) -------------------------------------------------------------------------------- Slack (setup path): 5.384ns (requirement - (data path - clock path skew + uncertainty)) Source: AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram (RAM) Destination: AD9249_spi_interface/gen_chipscope.LogicAnalyzer_SPI/U0/I_TQ0.G_TW[6].U_TQ (FF) Requirement: 10.000ns Data Path Delay: 4.070ns (Levels of Logic = 2) Clock Path Skew: -0.285ns (2.107 - 2.392) Source Clock: spi_2x_sclk rising at 5.000ns Destination Clock: debug_h1_20_OBUF rising at 15.000ns Clock Uncertainty: 0.261ns Clock Uncertainty: 0.261ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.272ns Phase Error (PE): 0.120ns Maximum Data Path at Slow Process Corner: AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram to AD9249_spi_interface/gen_chipscope.LogicAnalyzer_SPI/U0/I_TQ0.G_TW[6].U_TQ Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- RAMB18_X1Y5.DOBDO8 Trcko_DOB 1.784 AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram SLICE_X29Y18.C2 net (fanout=1) 1.047 AD9249_spi_interface/data_byte_out<6> SLICE_X29Y18.CMUX Tilo 0.308 AD9249_spi_interface/FPGA_master/data_cnt[2]_data_byte[7]_Mux_44_o AD9249_spi_interface/FPGA_master/Mmux_data_cnt[2]_data_byte[7]_Mux_44_o_3 AD9249_spi_interface/FPGA_master/Mmux_data_cnt[2]_data_byte[7]_Mux_44_o_2_f7 SLICE_X34Y28.C3 net (fanout=1) 0.871 AD9249_spi_interface/FPGA_master/data_cnt[2]_data_byte[7]_Mux_44_o SLICE_X34Y28.CLK Tas 0.060 AD9249_spi_interface/gen_chipscope.LogicAnalyzer_SPI/U0/iTRIG_IN<17> AD9249_spi_interface/FPGA_master/cur_state_sdo AD9249_spi_interface/gen_chipscope.LogicAnalyzer_SPI/U0/I_TQ0.G_TW[6].U_TQ ------------------------------------------------- --------------------------- Total 4.070ns (2.152ns logic, 1.918ns route) (52.9% logic, 47.1% route) -------------------------------------------------------------------------------- Slack (setup path): 5.489ns (requirement - (data path - clock path skew + uncertainty)) Source: AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram (RAM) Destination: AD9249_spi_interface/gen_chipscope.LogicAnalyzer_SPI/U0/I_TQ0.G_TW[6].U_TQ (FF) Requirement: 10.000ns Data Path Delay: 3.965ns (Levels of Logic = 2) Clock Path Skew: -0.285ns (2.107 - 2.392) Source Clock: spi_2x_sclk rising at 5.000ns Destination Clock: debug_h1_20_OBUF rising at 15.000ns Clock Uncertainty: 0.261ns Clock Uncertainty: 0.261ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.272ns Phase Error (PE): 0.120ns Maximum Data Path at Slow Process Corner: AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram to AD9249_spi_interface/gen_chipscope.LogicAnalyzer_SPI/U0/I_TQ0.G_TW[6].U_TQ Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- RAMB18_X1Y5.DOADO0 Trcko_DOA 1.784 AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram SLICE_X29Y18.D4 net (fanout=1) 0.946 AD9249_spi_interface/data_byte_out<0> SLICE_X29Y18.CMUX Topdc 0.304 AD9249_spi_interface/FPGA_master/data_cnt[2]_data_byte[7]_Mux_44_o AD9249_spi_interface/FPGA_master/Mmux_data_cnt[2]_data_byte[7]_Mux_44_o_4 AD9249_spi_interface/FPGA_master/Mmux_data_cnt[2]_data_byte[7]_Mux_44_o_2_f7 SLICE_X34Y28.C3 net (fanout=1) 0.871 AD9249_spi_interface/FPGA_master/data_cnt[2]_data_byte[7]_Mux_44_o SLICE_X34Y28.CLK Tas 0.060 AD9249_spi_interface/gen_chipscope.LogicAnalyzer_SPI/U0/iTRIG_IN<17> AD9249_spi_interface/FPGA_master/cur_state_sdo AD9249_spi_interface/gen_chipscope.LogicAnalyzer_SPI/U0/I_TQ0.G_TW[6].U_TQ ------------------------------------------------- --------------------------- Total 3.965ns (2.148ns logic, 1.817ns route) (54.2% logic, 45.8% route) -------------------------------------------------------------------------------- Paths for end point AD9249_spi_interface/gen_chipscope.LogicAnalyzer_SPI/U0/I_TQ0.G_TW[6].U_TQ (SLICE_X34Y28.C5), 27 paths -------------------------------------------------------------------------------- Slack (setup path): 5.498ns (requirement - (data path - clock path skew + uncertainty)) Source: AD9249_spi_interface/Instruction_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram (RAM) Destination: AD9249_spi_interface/gen_chipscope.LogicAnalyzer_SPI/U0/I_TQ0.G_TW[6].U_TQ (FF) Requirement: 10.000ns Data Path Delay: 3.927ns (Levels of Logic = 2) Clock Path Skew: -0.314ns (2.107 - 2.421) Source Clock: spi_2x_sclk rising at 5.000ns Destination Clock: debug_h1_20_OBUF rising at 15.000ns Clock Uncertainty: 0.261ns Clock Uncertainty: 0.261ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.272ns Phase Error (PE): 0.120ns Maximum Data Path at Slow Process Corner: AD9249_spi_interface/Instruction_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram to AD9249_spi_interface/gen_chipscope.LogicAnalyzer_SPI/U0/I_TQ0.G_TW[6].U_TQ Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- RAMB18_X2Y5.DOBDO8 Trcko_DOB 1.784 AD9249_spi_interface/Instruction_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram AD9249_spi_interface/Instruction_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram SLICE_X31Y17.A1 net (fanout=1) 1.003 AD9249_spi_interface/instr_bytes_out<12> SLICE_X31Y17.BMUX Topab 0.341 AD9249_spi_interface/FPGA_master/instr_cnt[3]_instr_bytes[15]_Mux_41_o AD9249_spi_interface/FPGA_master/Mmux_instr_cnt[3]_instr_bytes[15]_Mux_41_o_4 AD9249_spi_interface/FPGA_master/Mmux_instr_cnt[3]_instr_bytes[15]_Mux_41_o_3_f7 AD9249_spi_interface/FPGA_master/Mmux_instr_cnt[3]_instr_bytes[15]_Mux_41_o_2_f8 SLICE_X34Y28.C5 net (fanout=1) 0.739 AD9249_spi_interface/FPGA_master/instr_cnt[3]_instr_bytes[15]_Mux_41_o SLICE_X34Y28.CLK Tas 0.060 AD9249_spi_interface/gen_chipscope.LogicAnalyzer_SPI/U0/iTRIG_IN<17> AD9249_spi_interface/FPGA_master/cur_state_sdo AD9249_spi_interface/gen_chipscope.LogicAnalyzer_SPI/U0/I_TQ0.G_TW[6].U_TQ ------------------------------------------------- --------------------------- Total 3.927ns (2.185ns logic, 1.742ns route) (55.6% logic, 44.4% route) -------------------------------------------------------------------------------- Slack (setup path): 5.576ns (requirement - (data path - clock path skew + uncertainty)) Source: AD9249_spi_interface/Instruction_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram (RAM) Destination: AD9249_spi_interface/gen_chipscope.LogicAnalyzer_SPI/U0/I_TQ0.G_TW[6].U_TQ (FF) Requirement: 10.000ns Data Path Delay: 3.849ns (Levels of Logic = 2) Clock Path Skew: -0.314ns (2.107 - 2.421) Source Clock: spi_2x_sclk rising at 5.000ns Destination Clock: debug_h1_20_OBUF rising at 15.000ns Clock Uncertainty: 0.261ns Clock Uncertainty: 0.261ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.272ns Phase Error (PE): 0.120ns Maximum Data Path at Slow Process Corner: AD9249_spi_interface/Instruction_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram to AD9249_spi_interface/gen_chipscope.LogicAnalyzer_SPI/U0/I_TQ0.G_TW[6].U_TQ Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- RAMB18_X2Y5.DOADO3 Trcko_DOA 1.784 AD9249_spi_interface/Instruction_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram AD9249_spi_interface/Instruction_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram SLICE_X31Y17.D1 net (fanout=1) 0.912 AD9249_spi_interface/instr_bytes_out<3> SLICE_X31Y17.BMUX Topdb 0.354 AD9249_spi_interface/FPGA_master/instr_cnt[3]_instr_bytes[15]_Mux_41_o AD9249_spi_interface/FPGA_master/Mmux_instr_cnt[3]_instr_bytes[15]_Mux_41_o_6 AD9249_spi_interface/FPGA_master/Mmux_instr_cnt[3]_instr_bytes[15]_Mux_41_o_4_f7 AD9249_spi_interface/FPGA_master/Mmux_instr_cnt[3]_instr_bytes[15]_Mux_41_o_2_f8 SLICE_X34Y28.C5 net (fanout=1) 0.739 AD9249_spi_interface/FPGA_master/instr_cnt[3]_instr_bytes[15]_Mux_41_o SLICE_X34Y28.CLK Tas 0.060 AD9249_spi_interface/gen_chipscope.LogicAnalyzer_SPI/U0/iTRIG_IN<17> AD9249_spi_interface/FPGA_master/cur_state_sdo AD9249_spi_interface/gen_chipscope.LogicAnalyzer_SPI/U0/I_TQ0.G_TW[6].U_TQ ------------------------------------------------- --------------------------- Total 3.849ns (2.198ns logic, 1.651ns route) (57.1% logic, 42.9% route) -------------------------------------------------------------------------------- Slack (setup path): 5.595ns (requirement - (data path - clock path skew + uncertainty)) Source: AD9249_spi_interface/Instruction_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram (RAM) Destination: AD9249_spi_interface/gen_chipscope.LogicAnalyzer_SPI/U0/I_TQ0.G_TW[6].U_TQ (FF) Requirement: 10.000ns Data Path Delay: 3.830ns (Levels of Logic = 2) Clock Path Skew: -0.314ns (2.107 - 2.421) Source Clock: spi_2x_sclk rising at 5.000ns Destination Clock: debug_h1_20_OBUF rising at 15.000ns Clock Uncertainty: 0.261ns Clock Uncertainty: 0.261ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.272ns Phase Error (PE): 0.120ns Maximum Data Path at Slow Process Corner: AD9249_spi_interface/Instruction_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram to AD9249_spi_interface/gen_chipscope.LogicAnalyzer_SPI/U0/I_TQ0.G_TW[6].U_TQ Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- RAMB18_X2Y5.DOBDO3 Trcko_DOB 1.784 AD9249_spi_interface/Instruction_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram AD9249_spi_interface/Instruction_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram SLICE_X31Y17.B1 net (fanout=1) 0.911 AD9249_spi_interface/instr_bytes_out<11> SLICE_X31Y17.BMUX Topbb 0.336 AD9249_spi_interface/FPGA_master/instr_cnt[3]_instr_bytes[15]_Mux_41_o AD9249_spi_interface/FPGA_master/Mmux_instr_cnt[3]_instr_bytes[15]_Mux_41_o_5 AD9249_spi_interface/FPGA_master/Mmux_instr_cnt[3]_instr_bytes[15]_Mux_41_o_3_f7 AD9249_spi_interface/FPGA_master/Mmux_instr_cnt[3]_instr_bytes[15]_Mux_41_o_2_f8 SLICE_X34Y28.C5 net (fanout=1) 0.739 AD9249_spi_interface/FPGA_master/instr_cnt[3]_instr_bytes[15]_Mux_41_o SLICE_X34Y28.CLK Tas 0.060 AD9249_spi_interface/gen_chipscope.LogicAnalyzer_SPI/U0/iTRIG_IN<17> AD9249_spi_interface/FPGA_master/cur_state_sdo AD9249_spi_interface/gen_chipscope.LogicAnalyzer_SPI/U0/I_TQ0.G_TW[6].U_TQ ------------------------------------------------- --------------------------- Total 3.830ns (2.180ns logic, 1.650ns route) (56.9% logic, 43.1% route) -------------------------------------------------------------------------------- Paths for end point AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram (RAMB18_X1Y5.WEBWE0), 6 paths -------------------------------------------------------------------------------- Slack (setup path): 5.786ns (requirement - (data path - clock path skew + uncertainty)) Source: AD9249_spi_interface/gen_chipscope.VIO_SPI/U0/I_VIO/GEN_SYNC_OUT[18].SYNC_OUT_CELL/USER_REG (FF) Destination: AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram (RAM) Requirement: 10.000ns Data Path Delay: 4.100ns (Levels of Logic = 2) Clock Path Skew: -0.015ns (0.881 - 0.896) Source Clock: debug_h1_20_OBUF rising at 5.000ns Destination Clock: debug_h1_20_OBUF rising at 15.000ns Clock Uncertainty: 0.099ns Clock Uncertainty: 0.099ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.184ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: AD9249_spi_interface/gen_chipscope.VIO_SPI/U0/I_VIO/GEN_SYNC_OUT[18].SYNC_OUT_CELL/USER_REG to AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X37Y30.AQ Tcko 0.283 AD9249_spi_interface/vio_out<18> AD9249_spi_interface/gen_chipscope.VIO_SPI/U0/I_VIO/GEN_SYNC_OUT[18].SYNC_OUT_CELL/USER_REG SLICE_X32Y49.B2 net (fanout=8) 1.316 AD9249_spi_interface/vio_out<18> SLICE_X32Y49.B Tilo 0.061 AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<3> AD9249_spi_interface/Mmux_data_buf_wr_en_in11 SLICE_X33Y52.A6 net (fanout=2) 0.297 AD9249_spi_interface/data_buf_wr_en_in SLICE_X33Y52.A Tilo 0.061 AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/ram_wr_en_i1 RAMB18_X1Y5.WEBWE0 net (fanout=13) 1.613 AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en RAMB18_X1Y5.CLKBWRCLKTrcck_WEB 0.469 AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram ------------------------------------------------- --------------------------- Total 4.100ns (0.874ns logic, 3.226ns route) (21.3% logic, 78.7% route) -------------------------------------------------------------------------------- Slack (setup path): 6.165ns (requirement - (data path - clock path skew + uncertainty)) Source: cur_state_FSM_FFd2 (FF) Destination: AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram (RAM) Requirement: 10.000ns Data Path Delay: 3.742ns (Levels of Logic = 2) Clock Path Skew: 0.006ns (0.881 - 0.875) Source Clock: debug_h1_20_OBUF rising at 5.000ns Destination Clock: debug_h1_20_OBUF rising at 15.000ns Clock Uncertainty: 0.099ns Clock Uncertainty: 0.099ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.184ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: cur_state_FSM_FFd2 to AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X33Y30.BQ Tcko 0.283 cur_state_FSM_FFd3 cur_state_FSM_FFd2 SLICE_X32Y49.B4 net (fanout=12) 0.958 cur_state_FSM_FFd2 SLICE_X32Y49.B Tilo 0.061 AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<3> AD9249_spi_interface/Mmux_data_buf_wr_en_in11 SLICE_X33Y52.A6 net (fanout=2) 0.297 AD9249_spi_interface/data_buf_wr_en_in SLICE_X33Y52.A Tilo 0.061 AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/ram_wr_en_i1 RAMB18_X1Y5.WEBWE0 net (fanout=13) 1.613 AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en RAMB18_X1Y5.CLKBWRCLKTrcck_WEB 0.469 AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram ------------------------------------------------- --------------------------- Total 3.742ns (0.874ns logic, 2.868ns route) (23.4% logic, 76.6% route) -------------------------------------------------------------------------------- Slack (setup path): 6.208ns (requirement - (data path - clock path skew + uncertainty)) Source: cur_state_FSM_FFd1 (FF) Destination: AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram (RAM) Requirement: 10.000ns Data Path Delay: 3.699ns (Levels of Logic = 2) Clock Path Skew: 0.006ns (0.881 - 0.875) Source Clock: debug_h1_20_OBUF rising at 5.000ns Destination Clock: debug_h1_20_OBUF rising at 15.000ns Clock Uncertainty: 0.099ns Clock Uncertainty: 0.099ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.184ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: cur_state_FSM_FFd1 to AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X33Y30.AQ Tcko 0.283 cur_state_FSM_FFd3 cur_state_FSM_FFd1 SLICE_X32Y49.B6 net (fanout=11) 0.915 cur_state_FSM_FFd1 SLICE_X32Y49.B Tilo 0.061 AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1<3> AD9249_spi_interface/Mmux_data_buf_wr_en_in11 SLICE_X33Y52.A6 net (fanout=2) 0.297 AD9249_spi_interface/data_buf_wr_en_in SLICE_X33Y52.A Tilo 0.061 AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/ram_wr_en_i1 RAMB18_X1Y5.WEBWE0 net (fanout=13) 1.613 AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en RAMB18_X1Y5.CLKBWRCLKTrcck_WEB 0.469 AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram AD9249_spi_interface/Data_Fifo/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.WIDE_PRIM18.ram ------------------------------------------------- --------------------------- Total 3.699ns (0.874ns logic, 2.825ns route) (23.6% logic, 76.4% route) -------------------------------------------------------------------------------- Hold Paths: TS_System_clk_management_sys_clk = PERIOD TIMEGRP "System_clk_management_sys_clk" TS_evb_ref_clk_p LOW 50%; -------------------------------------------------------------------------------- Paths for end point AD9249_spi_interface/gen_chipscope.LogicAnalyzer_SPI/U0/I_TQ0.G_TW[3].U_TQ (SLICE_X35Y22.DX), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.019ns (requirement - (clock path skew + uncertainty - data path)) Source: AD9249_spi_interface/FPGA_master/sclk_net (FF) Destination: AD9249_spi_interface/gen_chipscope.LogicAnalyzer_SPI/U0/I_TQ0.G_TW[3].U_TQ (FF) Requirement: 0.000ns Data Path Delay: 0.408ns (Levels of Logic = 0) Clock Path Skew: 0.128ns (1.108 - 0.980) Source Clock: spi_2x_sclk rising at 5.000ns Destination Clock: debug_h1_20_OBUF rising at 5.000ns Clock Uncertainty: 0.261ns Clock Uncertainty: 0.261ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.272ns Phase Error (PE): 0.120ns Minimum Data Path at Fast Process Corner: AD9249_spi_interface/FPGA_master/sclk_net to AD9249_spi_interface/gen_chipscope.LogicAnalyzer_SPI/U0/I_TQ0.G_TW[3].U_TQ Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X37Y29.DQ Tcko 0.098 spi_sclk_OBUF AD9249_spi_interface/FPGA_master/sclk_net SLICE_X35Y22.DX net (fanout=6) 0.386 spi_sclk_OBUF SLICE_X35Y22.CLK Tckdi (-Th) 0.076 AD9249_spi_interface/gen_chipscope.LogicAnalyzer_SPI/U0/iTRIG_IN<3> AD9249_spi_interface/gen_chipscope.LogicAnalyzer_SPI/U0/I_TQ0.G_TW[3].U_TQ ------------------------------------------------- --------------------------- Total 0.408ns (0.022ns logic, 0.386ns route) (5.4% logic, 94.6% route) -------------------------------------------------------------------------------- Paths for end point cur_state_FSM_FFd1 (SLICE_X33Y30.A2), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.031ns (requirement - (clock path skew + uncertainty - data path)) Source: AD9249_spi_interface/FPGA_master/read_data_byte_reg_5 (FF) Destination: cur_state_FSM_FFd1 (FF) Requirement: 0.000ns Data Path Delay: 0.452ns (Levels of Logic = 1) Clock Path Skew: 0.160ns (1.116 - 0.956) Source Clock: spi_2x_sclk rising at 5.000ns Destination Clock: debug_h1_20_OBUF rising at 5.000ns Clock Uncertainty: 0.261ns Clock Uncertainty: 0.261ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.272ns Phase Error (PE): 0.120ns Minimum Data Path at Fast Process Corner: AD9249_spi_interface/FPGA_master/read_data_byte_reg_5 to cur_state_FSM_FFd1 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X29Y26.AQ Tcko 0.098 spi_read_data_byte<5> AD9249_spi_interface/FPGA_master/read_data_byte_reg_5 SLICE_X33Y30.A2 net (fanout=5) 0.409 spi_read_data_byte<5> SLICE_X33Y30.CLK Tah (-Th) 0.055 cur_state_FSM_FFd3 cur_state_FSM_FFd1-In1 cur_state_FSM_FFd1 ------------------------------------------------- --------------------------- Total 0.452ns (0.043ns logic, 0.409ns route) (9.5% logic, 90.5% route) -------------------------------------------------------------------------------- Paths for end point AD9249_dig_data_interface/gen_chipscope.LogicAnalyzer/U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[67].I_SRLT_NE_0.DLY9/SRL16E (SLICE_X30Y80.CX), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.038ns (requirement - (clock path skew + uncertainty - data path)) Source: AD9249_dig_data_interface/gen_chipscope.LogicAnalyzer/U0/I_TQ0.G_TW[67].U_TQ (FF) Destination: AD9249_dig_data_interface/gen_chipscope.LogicAnalyzer/U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[67].I_SRLT_NE_0.DLY9/SRL16E (FF) Requirement: 0.000ns Data Path Delay: 0.185ns (Levels of Logic = 0) Clock Path Skew: 0.147ns (0.719 - 0.572) Source Clock: debug_h1_20_OBUF rising at 15.000ns Destination Clock: debug_h1_20_OBUF rising at 15.000ns Clock Uncertainty: 0.000ns Minimum Data Path at Fast Process Corner: AD9249_dig_data_interface/gen_chipscope.LogicAnalyzer/U0/I_TQ0.G_TW[67].U_TQ to AD9249_dig_data_interface/gen_chipscope.LogicAnalyzer/U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[67].I_SRLT_NE_0.DLY9/SRL16E Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X30Y78.DQ Tcko 0.115 AD9249_dig_data_interface/gen_chipscope.LogicAnalyzer/U0/iTRIG_IN<67> AD9249_dig_data_interface/gen_chipscope.LogicAnalyzer/U0/I_TQ0.G_TW[67].U_TQ SLICE_X30Y80.CX net (fanout=2) 0.100 AD9249_dig_data_interface/gen_chipscope.LogicAnalyzer/U0/iTRIG_IN<67> SLICE_X30Y80.CLK Tdh (-Th) 0.030 AD9249_dig_data_interface/gen_chipscope.LogicAnalyzer/U0/I_NO_D.U_ILA/iDATA<66> AD9249_dig_data_interface/gen_chipscope.LogicAnalyzer/U0/I_NO_D.U_ILA/I_DQ.U_DQQ/DLY_9.DLY_9_GEN[67].I_SRLT_NE_0.DLY9/SRL16E ------------------------------------------------- --------------------------- Total 0.185ns (0.085ns logic, 0.100ns route) (45.9% logic, 54.1% route) -------------------------------------------------------------------------------- Component Switching Limit Checks: TS_System_clk_management_sys_clk = PERIOD TIMEGRP "System_clk_management_sys_clk" TS_evb_ref_clk_p LOW 50%; -------------------------------------------------------------------------------- Slack: 8.148ns (period - min period limit) Period: 10.000ns Min period limit: 1.852ns (539.957MHz) (Trper_CLKB) Physical resource: AD9249_spi_interface/gen_chipscope.LogicAnalyzer_SPI/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/CLKBWRCLKL Logical resource: AD9249_spi_interface/gen_chipscope.LogicAnalyzer_SPI/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/CLKBWRCLKL Location pin: RAMB36_X2Y4.CLKBWRCLKL Clock network: debug_h1_20_OBUF -------------------------------------------------------------------------------- Slack: 8.148ns (period - min period limit) Period: 10.000ns Min period limit: 1.852ns (539.957MHz) (Trper_CLKB) Physical resource: AD9249_dig_data_interface/gen_chipscope.LogicAnalyzer/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/CLKBWRCLKL Logical resource: AD9249_dig_data_interface/gen_chipscope.LogicAnalyzer/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/CLKBWRCLKL Location pin: RAMB36_X0Y19.CLKBWRCLKL Clock network: debug_h1_20_OBUF -------------------------------------------------------------------------------- Slack: 8.148ns (period - min period limit) Period: 10.000ns Min period limit: 1.852ns (539.957MHz) (Trper_CLKB) Physical resource: AD9249_spi_interface/gen_chipscope.LogicAnalyzer_SPI/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/CLKBWRCLKL Logical resource: AD9249_spi_interface/gen_chipscope.LogicAnalyzer_SPI/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[24].u_ramb36/U_RAMB36/CLKBWRCLKL Location pin: RAMB36_X0Y9.CLKBWRCLKL Clock network: debug_h1_20_OBUF -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TIMEGRP "din1_timegroup" OFFSET = IN 3 ns VALID 6 ns BEFORE COMP "DCO1_p" "RISING"; For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). 9 paths analyzed, 9 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) Offset is -0.542ns. -------------------------------------------------------------------------------- Paths for end point AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[2].ADC_channelXX_create_frame/Channel_DDR/iddr_inst (ILOGIC_X2Y113.DDLY), 1 path -------------------------------------------------------------------------------- Slack (setup path): 3.542ns (requirement - (data path - clock path - clock arrival + uncertainty)) Source: bank1_diff_ch_matrix<2><1> (PAD) Destination: AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[2].ADC_channelXX_create_frame/Channel_DDR/iddr_inst (FF) Destination Clock: AD9249_dig_data_interface/DCO_1_BUFG rising at 0.000ns Requirement: 3.000ns Data Path Delay: 2.252ns (Levels of Logic = 1) Clock Path Delay: 2.819ns (Levels of Logic = 2) Clock Uncertainty: 0.025ns Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Fast Process Corner: bank1_diff_ch_matrix<2><1> to AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[2].ADC_channelXX_create_frame/Channel_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- A7.I Tiopi 0.647 bank1_diff_ch_matrix<2><1> bank1_diff_ch_matrix<2><1> AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[2].ADC_channelXX_create_frame/IB/IBUFDS ILOGIC_X2Y113.DDLY net (fanout=1) 1.508 AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[2].ADC_channelXX_create_frame/ch_in ILOGIC_X2Y113.CLK Tidockd 0.097 AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[2].ADC_channelXX_create_frame/channel_nib<1> AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[2].ADC_channelXX_create_frame/Channel_DDR/iddr_inst ------------------------------------------------- --------------------------- Total 2.252ns (0.744ns logic, 1.508ns route) (33.0% logic, 67.0% route) Minimum Clock Path at Fast Process Corner: DCO1_p to AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[2].ADC_channelXX_create_frame/Channel_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- F7.I Tiopi 0.535 DCO1_p DCO1_p AD9249_dig_data_interface/IB_DCO1/IBUFDS BUFGCTRL_X0Y30.I0 net (fanout=3) 1.572 debug_header_14_OBUF BUFGCTRL_X0Y30.O Tbgcko_O 0.033 AD9249_dig_data_interface/DCO_1_BUFG AD9249_dig_data_interface/DCO_1_BUFG ILOGIC_X2Y113.CLK net (fanout=101) 0.679 AD9249_dig_data_interface/DCO_1_BUFG ------------------------------------------------- --------------------------- Total 2.819ns (0.568ns logic, 2.251ns route) (20.1% logic, 79.9% route) -------------------------------------------------------------------------------- Paths for end point AD9249_dig_data_interface/ADC_bank1/FCO_DDR/iddr_inst (ILOGIC_X2Y117.DDLY), 1 path -------------------------------------------------------------------------------- Slack (setup path): 3.553ns (requirement - (data path - clock path - clock arrival + uncertainty)) Source: FCO1_p (PAD) Destination: AD9249_dig_data_interface/ADC_bank1/FCO_DDR/iddr_inst (FF) Destination Clock: AD9249_dig_data_interface/DCO_1_BUFG rising at 0.000ns Requirement: 3.000ns Data Path Delay: 2.251ns (Levels of Logic = 1) Clock Path Delay: 2.829ns (Levels of Logic = 2) Clock Uncertainty: 0.025ns Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Fast Process Corner: FCO1_p to AD9249_dig_data_interface/ADC_bank1/FCO_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- B8.I Tiopi 0.646 FCO1_p FCO1_p AD9249_dig_data_interface/IB_FCO1/IBUFDS ILOGIC_X2Y117.DDLY net (fanout=2) 1.508 debug_header_17_OBUF ILOGIC_X2Y117.CLK Tidockd 0.097 AD9249_dig_data_interface/ADC_bank1/fco_data_nib<1> AD9249_dig_data_interface/ADC_bank1/FCO_DDR/iddr_inst ------------------------------------------------- --------------------------- Total 2.251ns (0.743ns logic, 1.508ns route) (33.0% logic, 67.0% route) Minimum Clock Path at Fast Process Corner: DCO1_p to AD9249_dig_data_interface/ADC_bank1/FCO_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- F7.I Tiopi 0.535 DCO1_p DCO1_p AD9249_dig_data_interface/IB_DCO1/IBUFDS BUFGCTRL_X0Y30.I0 net (fanout=3) 1.572 debug_header_14_OBUF BUFGCTRL_X0Y30.O Tbgcko_O 0.033 AD9249_dig_data_interface/DCO_1_BUFG AD9249_dig_data_interface/DCO_1_BUFG ILOGIC_X2Y117.CLK net (fanout=101) 0.689 AD9249_dig_data_interface/DCO_1_BUFG ------------------------------------------------- --------------------------- Total 2.829ns (0.568ns logic, 2.261ns route) (20.1% logic, 79.9% route) -------------------------------------------------------------------------------- Paths for end point AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[4].ADC_channelXX_create_frame/Channel_DDR/iddr_inst (ILOGIC_X2Y105.DDLY), 1 path -------------------------------------------------------------------------------- Slack (setup path): 3.563ns (requirement - (data path - clock path - clock arrival + uncertainty)) Source: bank1_diff_ch_matrix<4><1> (PAD) Destination: AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[4].ADC_channelXX_create_frame/Channel_DDR/iddr_inst (FF) Destination Clock: AD9249_dig_data_interface/DCO_1_BUFG rising at 0.000ns Requirement: 3.000ns Data Path Delay: 2.231ns (Levels of Logic = 1) Clock Path Delay: 2.819ns (Levels of Logic = 2) Clock Uncertainty: 0.025ns Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Fast Process Corner: bank1_diff_ch_matrix<4><1> to AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[4].ADC_channelXX_create_frame/Channel_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- E8.I Tiopi 0.626 bank1_diff_ch_matrix<4><1> bank1_diff_ch_matrix<4><1> AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[4].ADC_channelXX_create_frame/IB/IBUFDS ILOGIC_X2Y105.DDLY net (fanout=1) 1.508 AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[4].ADC_channelXX_create_frame/ch_in ILOGIC_X2Y105.CLK Tidockd 0.097 AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[4].ADC_channelXX_create_frame/channel_nib<1> AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[4].ADC_channelXX_create_frame/Channel_DDR/iddr_inst ------------------------------------------------- --------------------------- Total 2.231ns (0.723ns logic, 1.508ns route) (32.4% logic, 67.6% route) Minimum Clock Path at Fast Process Corner: DCO1_p to AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[4].ADC_channelXX_create_frame/Channel_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- F7.I Tiopi 0.535 DCO1_p DCO1_p AD9249_dig_data_interface/IB_DCO1/IBUFDS BUFGCTRL_X0Y30.I0 net (fanout=3) 1.572 debug_header_14_OBUF BUFGCTRL_X0Y30.O Tbgcko_O 0.033 AD9249_dig_data_interface/DCO_1_BUFG AD9249_dig_data_interface/DCO_1_BUFG ILOGIC_X2Y105.CLK net (fanout=101) 0.679 AD9249_dig_data_interface/DCO_1_BUFG ------------------------------------------------- --------------------------- Total 2.819ns (0.568ns logic, 2.251ns route) (20.1% logic, 79.9% route) -------------------------------------------------------------------------------- Hold Paths: TIMEGRP "din1_timegroup" OFFSET = IN 3 ns VALID 6 ns BEFORE COMP "DCO1_p" "RISING"; -------------------------------------------------------------------------------- Paths for end point AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[0].ADC_channelXX_create_frame/Channel_DDR/iddr_inst (ILOGIC_X2Y97.DDLY), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.639ns (requirement - (clock path + clock arrival + uncertainty - data path)) Source: bank1_diff_ch_matrix<0><1> (PAD) Destination: AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[0].ADC_channelXX_create_frame/Channel_DDR/iddr_inst (FF) Destination Clock: AD9249_dig_data_interface/DCO_1_BUFG rising at 0.000ns Requirement: 3.000ns Data Path Delay: 3.569ns (Levels of Logic = 1) Clock Path Delay: 5.905ns (Levels of Logic = 2) Clock Uncertainty: 0.025ns Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Minimum Data Path at Slow Process Corner: bank1_diff_ch_matrix<0><1> to AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[0].ADC_channelXX_create_frame/Channel_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- J12.I Tiopi 0.920 bank1_diff_ch_matrix<0><1> bank1_diff_ch_matrix<0><1> AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[0].ADC_channelXX_create_frame/IB/IBUFDS ILOGIC_X2Y97.DDLY net (fanout=1) 2.702 AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[0].ADC_channelXX_create_frame/ch_in ILOGIC_X2Y97.CLK Tiockdd (-Th) 0.053 AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[0].ADC_channelXX_create_frame/channel_nib<1> AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[0].ADC_channelXX_create_frame/Channel_DDR/iddr_inst ------------------------------------------------- --------------------------- Total 3.569ns (0.867ns logic, 2.702ns route) (24.3% logic, 75.7% route) Maximum Clock Path at Slow Process Corner: DCO1_p to AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[0].ADC_channelXX_create_frame/Channel_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- F7.I Tiopi 0.998 DCO1_p DCO1_p AD9249_dig_data_interface/IB_DCO1/IBUFDS BUFGCTRL_X0Y30.I0 net (fanout=3) 3.154 debug_header_14_OBUF BUFGCTRL_X0Y30.O Tbgcko_O 0.079 AD9249_dig_data_interface/DCO_1_BUFG AD9249_dig_data_interface/DCO_1_BUFG ILOGIC_X2Y97.CLK net (fanout=101) 1.674 AD9249_dig_data_interface/DCO_1_BUFG ------------------------------------------------- --------------------------- Total 5.905ns (1.077ns logic, 4.828ns route) (18.2% logic, 81.8% route) -------------------------------------------------------------------------------- Paths for end point AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[1].ADC_channelXX_create_frame/Channel_DDR/iddr_inst (ILOGIC_X2Y119.DDLY), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.639ns (requirement - (clock path + clock arrival + uncertainty - data path)) Source: bank1_diff_ch_matrix<1><1> (PAD) Destination: AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[1].ADC_channelXX_create_frame/Channel_DDR/iddr_inst (FF) Destination Clock: AD9249_dig_data_interface/DCO_1_BUFG rising at 0.000ns Requirement: 3.000ns Data Path Delay: 3.580ns (Levels of Logic = 1) Clock Path Delay: 5.916ns (Levels of Logic = 2) Clock Uncertainty: 0.025ns Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Minimum Data Path at Slow Process Corner: bank1_diff_ch_matrix<1><1> to AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[1].ADC_channelXX_create_frame/Channel_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- F11.I Tiopi 0.931 bank1_diff_ch_matrix<1><1> bank1_diff_ch_matrix<1><1> AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[1].ADC_channelXX_create_frame/IB/IBUFDS ILOGIC_X2Y119.DDLY net (fanout=1) 2.702 AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[1].ADC_channelXX_create_frame/ch_in ILOGIC_X2Y119.CLK Tiockdd (-Th) 0.053 AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[1].ADC_channelXX_create_frame/channel_nib<1> AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[1].ADC_channelXX_create_frame/Channel_DDR/iddr_inst ------------------------------------------------- --------------------------- Total 3.580ns (0.878ns logic, 2.702ns route) (24.5% logic, 75.5% route) Maximum Clock Path at Slow Process Corner: DCO1_p to AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[1].ADC_channelXX_create_frame/Channel_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- F7.I Tiopi 0.998 DCO1_p DCO1_p AD9249_dig_data_interface/IB_DCO1/IBUFDS BUFGCTRL_X0Y30.I0 net (fanout=3) 3.154 debug_header_14_OBUF BUFGCTRL_X0Y30.O Tbgcko_O 0.079 AD9249_dig_data_interface/DCO_1_BUFG AD9249_dig_data_interface/DCO_1_BUFG ILOGIC_X2Y119.CLK net (fanout=101) 1.685 AD9249_dig_data_interface/DCO_1_BUFG ------------------------------------------------- --------------------------- Total 5.916ns (1.077ns logic, 4.839ns route) (18.2% logic, 81.8% route) -------------------------------------------------------------------------------- Paths for end point AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[3].ADC_channelXX_create_frame/Channel_DDR/iddr_inst (ILOGIC_X2Y107.DDLY), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.646ns (requirement - (clock path + clock arrival + uncertainty - data path)) Source: bank1_diff_ch_matrix<3><1> (PAD) Destination: AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[3].ADC_channelXX_create_frame/Channel_DDR/iddr_inst (FF) Destination Clock: AD9249_dig_data_interface/DCO_1_BUFG rising at 0.000ns Requirement: 3.000ns Data Path Delay: 3.576ns (Levels of Logic = 1) Clock Path Delay: 5.905ns (Levels of Logic = 2) Clock Uncertainty: 0.025ns Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Minimum Data Path at Slow Process Corner: bank1_diff_ch_matrix<3><1> to AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[3].ADC_channelXX_create_frame/Channel_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- G11.I Tiopi 0.927 bank1_diff_ch_matrix<3><1> bank1_diff_ch_matrix<3><1> AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[3].ADC_channelXX_create_frame/IB/IBUFDS ILOGIC_X2Y107.DDLY net (fanout=1) 2.702 AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[3].ADC_channelXX_create_frame/ch_in ILOGIC_X2Y107.CLK Tiockdd (-Th) 0.053 AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[3].ADC_channelXX_create_frame/channel_nib<1> AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[3].ADC_channelXX_create_frame/Channel_DDR/iddr_inst ------------------------------------------------- --------------------------- Total 3.576ns (0.874ns logic, 2.702ns route) (24.4% logic, 75.6% route) Maximum Clock Path at Slow Process Corner: DCO1_p to AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[3].ADC_channelXX_create_frame/Channel_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- F7.I Tiopi 0.998 DCO1_p DCO1_p AD9249_dig_data_interface/IB_DCO1/IBUFDS BUFGCTRL_X0Y30.I0 net (fanout=3) 3.154 debug_header_14_OBUF BUFGCTRL_X0Y30.O Tbgcko_O 0.079 AD9249_dig_data_interface/DCO_1_BUFG AD9249_dig_data_interface/DCO_1_BUFG ILOGIC_X2Y107.CLK net (fanout=101) 1.674 AD9249_dig_data_interface/DCO_1_BUFG ------------------------------------------------- --------------------------- Total 5.905ns (1.077ns logic, 4.828ns route) (18.2% logic, 81.8% route) -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TIMEGRP "din1_timegroup" OFFSET = IN 3 ns VALID 6 ns BEFORE COMP "DCO1_p" "FALLING"; For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). 9 paths analyzed, 9 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) Offset is -0.541ns. -------------------------------------------------------------------------------- Paths for end point AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[2].ADC_channelXX_create_frame/Channel_DDR/iddr_inst (ILOGIC_X2Y113.DDLY), 1 path -------------------------------------------------------------------------------- Slack (setup path): 3.541ns (requirement - (data path - clock path - clock arrival + uncertainty)) Source: bank1_diff_ch_matrix<2><1> (PAD) Destination: AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[2].ADC_channelXX_create_frame/Channel_DDR/iddr_inst (FF) Destination Clock: AD9249_dig_data_interface/DCO_1_BUFG falling at 0.000ns Requirement: 3.000ns Data Path Delay: 2.253ns (Levels of Logic = 1) Clock Path Delay: 2.819ns (Levels of Logic = 2) Clock Uncertainty: 0.025ns Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Fast Process Corner: bank1_diff_ch_matrix<2><1> to AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[2].ADC_channelXX_create_frame/Channel_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- A7.I Tiopi 0.647 bank1_diff_ch_matrix<2><1> bank1_diff_ch_matrix<2><1> AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[2].ADC_channelXX_create_frame/IB/IBUFDS ILOGIC_X2Y113.DDLY net (fanout=1) 1.508 AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[2].ADC_channelXX_create_frame/ch_in ILOGIC_X2Y113.CLKB Tidockd 0.098 AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[2].ADC_channelXX_create_frame/channel_nib<1> AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[2].ADC_channelXX_create_frame/Channel_DDR/iddr_inst ------------------------------------------------- --------------------------- Total 2.253ns (0.745ns logic, 1.508ns route) (33.1% logic, 66.9% route) Minimum Clock Path at Fast Process Corner: DCO1_p to AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[2].ADC_channelXX_create_frame/Channel_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- F7.I Tiopi 0.535 DCO1_p DCO1_p AD9249_dig_data_interface/IB_DCO1/IBUFDS BUFGCTRL_X0Y30.I0 net (fanout=3) 1.572 debug_header_14_OBUF BUFGCTRL_X0Y30.O Tbgcko_O 0.033 AD9249_dig_data_interface/DCO_1_BUFG AD9249_dig_data_interface/DCO_1_BUFG ILOGIC_X2Y113.CLKB net (fanout=101) 0.679 AD9249_dig_data_interface/DCO_1_BUFG ------------------------------------------------- --------------------------- Total 2.819ns (0.568ns logic, 2.251ns route) (20.1% logic, 79.9% route) -------------------------------------------------------------------------------- Paths for end point AD9249_dig_data_interface/ADC_bank1/FCO_DDR/iddr_inst (ILOGIC_X2Y117.DDLY), 1 path -------------------------------------------------------------------------------- Slack (setup path): 3.552ns (requirement - (data path - clock path - clock arrival + uncertainty)) Source: FCO1_p (PAD) Destination: AD9249_dig_data_interface/ADC_bank1/FCO_DDR/iddr_inst (FF) Destination Clock: AD9249_dig_data_interface/DCO_1_BUFG falling at 0.000ns Requirement: 3.000ns Data Path Delay: 2.252ns (Levels of Logic = 1) Clock Path Delay: 2.829ns (Levels of Logic = 2) Clock Uncertainty: 0.025ns Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Fast Process Corner: FCO1_p to AD9249_dig_data_interface/ADC_bank1/FCO_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- B8.I Tiopi 0.646 FCO1_p FCO1_p AD9249_dig_data_interface/IB_FCO1/IBUFDS ILOGIC_X2Y117.DDLY net (fanout=2) 1.508 debug_header_17_OBUF ILOGIC_X2Y117.CLKB Tidockd 0.098 AD9249_dig_data_interface/ADC_bank1/fco_data_nib<1> AD9249_dig_data_interface/ADC_bank1/FCO_DDR/iddr_inst ------------------------------------------------- --------------------------- Total 2.252ns (0.744ns logic, 1.508ns route) (33.0% logic, 67.0% route) Minimum Clock Path at Fast Process Corner: DCO1_p to AD9249_dig_data_interface/ADC_bank1/FCO_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- F7.I Tiopi 0.535 DCO1_p DCO1_p AD9249_dig_data_interface/IB_DCO1/IBUFDS BUFGCTRL_X0Y30.I0 net (fanout=3) 1.572 debug_header_14_OBUF BUFGCTRL_X0Y30.O Tbgcko_O 0.033 AD9249_dig_data_interface/DCO_1_BUFG AD9249_dig_data_interface/DCO_1_BUFG ILOGIC_X2Y117.CLKB net (fanout=101) 0.689 AD9249_dig_data_interface/DCO_1_BUFG ------------------------------------------------- --------------------------- Total 2.829ns (0.568ns logic, 2.261ns route) (20.1% logic, 79.9% route) -------------------------------------------------------------------------------- Paths for end point AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[4].ADC_channelXX_create_frame/Channel_DDR/iddr_inst (ILOGIC_X2Y105.DDLY), 1 path -------------------------------------------------------------------------------- Slack (setup path): 3.562ns (requirement - (data path - clock path - clock arrival + uncertainty)) Source: bank1_diff_ch_matrix<4><1> (PAD) Destination: AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[4].ADC_channelXX_create_frame/Channel_DDR/iddr_inst (FF) Destination Clock: AD9249_dig_data_interface/DCO_1_BUFG falling at 0.000ns Requirement: 3.000ns Data Path Delay: 2.232ns (Levels of Logic = 1) Clock Path Delay: 2.819ns (Levels of Logic = 2) Clock Uncertainty: 0.025ns Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Fast Process Corner: bank1_diff_ch_matrix<4><1> to AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[4].ADC_channelXX_create_frame/Channel_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- E8.I Tiopi 0.626 bank1_diff_ch_matrix<4><1> bank1_diff_ch_matrix<4><1> AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[4].ADC_channelXX_create_frame/IB/IBUFDS ILOGIC_X2Y105.DDLY net (fanout=1) 1.508 AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[4].ADC_channelXX_create_frame/ch_in ILOGIC_X2Y105.CLKB Tidockd 0.098 AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[4].ADC_channelXX_create_frame/channel_nib<1> AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[4].ADC_channelXX_create_frame/Channel_DDR/iddr_inst ------------------------------------------------- --------------------------- Total 2.232ns (0.724ns logic, 1.508ns route) (32.4% logic, 67.6% route) Minimum Clock Path at Fast Process Corner: DCO1_p to AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[4].ADC_channelXX_create_frame/Channel_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- F7.I Tiopi 0.535 DCO1_p DCO1_p AD9249_dig_data_interface/IB_DCO1/IBUFDS BUFGCTRL_X0Y30.I0 net (fanout=3) 1.572 debug_header_14_OBUF BUFGCTRL_X0Y30.O Tbgcko_O 0.033 AD9249_dig_data_interface/DCO_1_BUFG AD9249_dig_data_interface/DCO_1_BUFG ILOGIC_X2Y105.CLKB net (fanout=101) 0.679 AD9249_dig_data_interface/DCO_1_BUFG ------------------------------------------------- --------------------------- Total 2.819ns (0.568ns logic, 2.251ns route) (20.1% logic, 79.9% route) -------------------------------------------------------------------------------- Hold Paths: TIMEGRP "din1_timegroup" OFFSET = IN 3 ns VALID 6 ns BEFORE COMP "DCO1_p" "FALLING"; -------------------------------------------------------------------------------- Paths for end point AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[0].ADC_channelXX_create_frame/Channel_DDR/iddr_inst (ILOGIC_X2Y97.DDLY), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.641ns (requirement - (clock path + clock arrival + uncertainty - data path)) Source: bank1_diff_ch_matrix<0><1> (PAD) Destination: AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[0].ADC_channelXX_create_frame/Channel_DDR/iddr_inst (FF) Destination Clock: AD9249_dig_data_interface/DCO_1_BUFG falling at 0.000ns Requirement: 3.000ns Data Path Delay: 3.571ns (Levels of Logic = 1) Clock Path Delay: 5.905ns (Levels of Logic = 2) Clock Uncertainty: 0.025ns Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Minimum Data Path at Slow Process Corner: bank1_diff_ch_matrix<0><1> to AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[0].ADC_channelXX_create_frame/Channel_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- J12.I Tiopi 0.920 bank1_diff_ch_matrix<0><1> bank1_diff_ch_matrix<0><1> AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[0].ADC_channelXX_create_frame/IB/IBUFDS ILOGIC_X2Y97.DDLY net (fanout=1) 2.702 AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[0].ADC_channelXX_create_frame/ch_in ILOGIC_X2Y97.CLKB Tiockdd (-Th) 0.051 AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[0].ADC_channelXX_create_frame/channel_nib<1> AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[0].ADC_channelXX_create_frame/Channel_DDR/iddr_inst ------------------------------------------------- --------------------------- Total 3.571ns (0.869ns logic, 2.702ns route) (24.3% logic, 75.7% route) Maximum Clock Path at Slow Process Corner: DCO1_p to AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[0].ADC_channelXX_create_frame/Channel_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- F7.I Tiopi 0.998 DCO1_p DCO1_p AD9249_dig_data_interface/IB_DCO1/IBUFDS BUFGCTRL_X0Y30.I0 net (fanout=3) 3.154 debug_header_14_OBUF BUFGCTRL_X0Y30.O Tbgcko_O 0.079 AD9249_dig_data_interface/DCO_1_BUFG AD9249_dig_data_interface/DCO_1_BUFG ILOGIC_X2Y97.CLKB net (fanout=101) 1.674 AD9249_dig_data_interface/DCO_1_BUFG ------------------------------------------------- --------------------------- Total 5.905ns (1.077ns logic, 4.828ns route) (18.2% logic, 81.8% route) -------------------------------------------------------------------------------- Paths for end point AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[1].ADC_channelXX_create_frame/Channel_DDR/iddr_inst (ILOGIC_X2Y119.DDLY), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.641ns (requirement - (clock path + clock arrival + uncertainty - data path)) Source: bank1_diff_ch_matrix<1><1> (PAD) Destination: AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[1].ADC_channelXX_create_frame/Channel_DDR/iddr_inst (FF) Destination Clock: AD9249_dig_data_interface/DCO_1_BUFG falling at 0.000ns Requirement: 3.000ns Data Path Delay: 3.582ns (Levels of Logic = 1) Clock Path Delay: 5.916ns (Levels of Logic = 2) Clock Uncertainty: 0.025ns Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Minimum Data Path at Slow Process Corner: bank1_diff_ch_matrix<1><1> to AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[1].ADC_channelXX_create_frame/Channel_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- F11.I Tiopi 0.931 bank1_diff_ch_matrix<1><1> bank1_diff_ch_matrix<1><1> AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[1].ADC_channelXX_create_frame/IB/IBUFDS ILOGIC_X2Y119.DDLY net (fanout=1) 2.702 AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[1].ADC_channelXX_create_frame/ch_in ILOGIC_X2Y119.CLKB Tiockdd (-Th) 0.051 AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[1].ADC_channelXX_create_frame/channel_nib<1> AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[1].ADC_channelXX_create_frame/Channel_DDR/iddr_inst ------------------------------------------------- --------------------------- Total 3.582ns (0.880ns logic, 2.702ns route) (24.6% logic, 75.4% route) Maximum Clock Path at Slow Process Corner: DCO1_p to AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[1].ADC_channelXX_create_frame/Channel_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- F7.I Tiopi 0.998 DCO1_p DCO1_p AD9249_dig_data_interface/IB_DCO1/IBUFDS BUFGCTRL_X0Y30.I0 net (fanout=3) 3.154 debug_header_14_OBUF BUFGCTRL_X0Y30.O Tbgcko_O 0.079 AD9249_dig_data_interface/DCO_1_BUFG AD9249_dig_data_interface/DCO_1_BUFG ILOGIC_X2Y119.CLKB net (fanout=101) 1.685 AD9249_dig_data_interface/DCO_1_BUFG ------------------------------------------------- --------------------------- Total 5.916ns (1.077ns logic, 4.839ns route) (18.2% logic, 81.8% route) -------------------------------------------------------------------------------- Paths for end point AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[3].ADC_channelXX_create_frame/Channel_DDR/iddr_inst (ILOGIC_X2Y107.DDLY), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.648ns (requirement - (clock path + clock arrival + uncertainty - data path)) Source: bank1_diff_ch_matrix<3><1> (PAD) Destination: AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[3].ADC_channelXX_create_frame/Channel_DDR/iddr_inst (FF) Destination Clock: AD9249_dig_data_interface/DCO_1_BUFG falling at 0.000ns Requirement: 3.000ns Data Path Delay: 3.578ns (Levels of Logic = 1) Clock Path Delay: 5.905ns (Levels of Logic = 2) Clock Uncertainty: 0.025ns Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Minimum Data Path at Slow Process Corner: bank1_diff_ch_matrix<3><1> to AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[3].ADC_channelXX_create_frame/Channel_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- G11.I Tiopi 0.927 bank1_diff_ch_matrix<3><1> bank1_diff_ch_matrix<3><1> AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[3].ADC_channelXX_create_frame/IB/IBUFDS ILOGIC_X2Y107.DDLY net (fanout=1) 2.702 AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[3].ADC_channelXX_create_frame/ch_in ILOGIC_X2Y107.CLKB Tiockdd (-Th) 0.051 AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[3].ADC_channelXX_create_frame/channel_nib<1> AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[3].ADC_channelXX_create_frame/Channel_DDR/iddr_inst ------------------------------------------------- --------------------------- Total 3.578ns (0.876ns logic, 2.702ns route) (24.5% logic, 75.5% route) Maximum Clock Path at Slow Process Corner: DCO1_p to AD9249_dig_data_interface/ADC_bank1/generate_channel_bank[3].ADC_channelXX_create_frame/Channel_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- F7.I Tiopi 0.998 DCO1_p DCO1_p AD9249_dig_data_interface/IB_DCO1/IBUFDS BUFGCTRL_X0Y30.I0 net (fanout=3) 3.154 debug_header_14_OBUF BUFGCTRL_X0Y30.O Tbgcko_O 0.079 AD9249_dig_data_interface/DCO_1_BUFG AD9249_dig_data_interface/DCO_1_BUFG ILOGIC_X2Y107.CLKB net (fanout=101) 1.674 AD9249_dig_data_interface/DCO_1_BUFG ------------------------------------------------- --------------------------- Total 5.905ns (1.077ns logic, 4.828ns route) (18.2% logic, 81.8% route) -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TIMEGRP "din2_timegroup" OFFSET = IN 3 ns VALID 6 ns BEFORE COMP "DCO2_p" "RISING"; For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). 9 paths analyzed, 9 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) Minimum allowable offset is 0.762ns. -------------------------------------------------------------------------------- Paths for end point AD9249_dig_data_interface/ADC_bank2/FCO_DDR/iddr_inst (ILOGIC_X2Y95.DDLY), 1 path -------------------------------------------------------------------------------- Slack (setup path): 2.238ns (requirement - (data path - clock path - clock arrival + uncertainty)) Source: FCO2_p (PAD) Destination: AD9249_dig_data_interface/ADC_bank2/FCO_DDR/iddr_inst (FF) Destination Clock: AD9249_dig_data_interface/DCO_2_BUFG rising at 0.000ns Requirement: 3.000ns Data Path Delay: 4.318ns (Levels of Logic = 1) Clock Path Delay: 3.581ns (Levels of Logic = 2) Clock Uncertainty: 0.025ns Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: FCO2_p to AD9249_dig_data_interface/ADC_bank2/FCO_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- B9.I Tiopi 1.014 FCO2_p FCO2_p AD9249_dig_data_interface/IB_FCO2/IBUFDS ILOGIC_X2Y95.DDLY net (fanout=1) 3.191 AD9249_dig_data_interface/FCO_2 ILOGIC_X2Y95.CLK Tidockd 0.113 AD9249_dig_data_interface/ADC_bank2/fco_data_nib<1> AD9249_dig_data_interface/ADC_bank2/FCO_DDR/iddr_inst ------------------------------------------------- --------------------------- Total 4.318ns (1.127ns logic, 3.191ns route) (26.1% logic, 73.9% route) Minimum Clock Path at Slow Process Corner: DCO2_p to AD9249_dig_data_interface/ADC_bank2/FCO_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- H11.I Tiopi 0.929 DCO2_p DCO2_p AD9249_dig_data_interface/IB_DCO2/IBUFDS BUFGCTRL_X0Y31.I0 net (fanout=1) 1.091 AD9249_dig_data_interface/DCO_2 BUFGCTRL_X0Y31.O Tbgcko_O 0.074 AD9249_dig_data_interface/DCO_2_BUFG AD9249_dig_data_interface/DCO_2_BUFG ILOGIC_X2Y95.CLK net (fanout=97) 1.487 AD9249_dig_data_interface/DCO_2_BUFG ------------------------------------------------- --------------------------- Total 3.581ns (1.003ns logic, 2.578ns route) (28.0% logic, 72.0% route) -------------------------------------------------------------------------------- Paths for end point AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[4].ADC_channelXX_create_frame/Channel_DDR/iddr_inst (ILOGIC_X2Y91.DDLY), 1 path -------------------------------------------------------------------------------- Slack (setup path): 2.239ns (requirement - (data path - clock path - clock arrival + uncertainty)) Source: bank2_diff_ch_matrix<4><1> (PAD) Destination: AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[4].ADC_channelXX_create_frame/Channel_DDR/iddr_inst (FF) Destination Clock: AD9249_dig_data_interface/DCO_2_BUFG rising at 0.000ns Requirement: 3.000ns Data Path Delay: 4.317ns (Levels of Logic = 1) Clock Path Delay: 3.581ns (Levels of Logic = 2) Clock Uncertainty: 0.025ns Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: bank2_diff_ch_matrix<4><1> to AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[4].ADC_channelXX_create_frame/Channel_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- D7.I Tiopi 1.013 bank2_diff_ch_matrix<4><1> bank2_diff_ch_matrix<4><1> AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[4].ADC_channelXX_create_frame/IB/IBUFDS ILOGIC_X2Y91.DDLY net (fanout=1) 3.191 AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[4].ADC_channelXX_create_frame/ch_in ILOGIC_X2Y91.CLK Tidockd 0.113 AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[4].ADC_channelXX_create_frame/channel_nib<1> AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[4].ADC_channelXX_create_frame/Channel_DDR/iddr_inst ------------------------------------------------- --------------------------- Total 4.317ns (1.126ns logic, 3.191ns route) (26.1% logic, 73.9% route) Minimum Clock Path at Slow Process Corner: DCO2_p to AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[4].ADC_channelXX_create_frame/Channel_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- H11.I Tiopi 0.929 DCO2_p DCO2_p AD9249_dig_data_interface/IB_DCO2/IBUFDS BUFGCTRL_X0Y31.I0 net (fanout=1) 1.091 AD9249_dig_data_interface/DCO_2 BUFGCTRL_X0Y31.O Tbgcko_O 0.074 AD9249_dig_data_interface/DCO_2_BUFG AD9249_dig_data_interface/DCO_2_BUFG ILOGIC_X2Y91.CLK net (fanout=97) 1.487 AD9249_dig_data_interface/DCO_2_BUFG ------------------------------------------------- --------------------------- Total 3.581ns (1.003ns logic, 2.578ns route) (28.0% logic, 72.0% route) -------------------------------------------------------------------------------- Paths for end point AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[1].ADC_channelXX_create_frame/Channel_DDR/iddr_inst (ILOGIC_X2Y115.DDLY), 1 path -------------------------------------------------------------------------------- Slack (setup path): 2.251ns (requirement - (data path - clock path - clock arrival + uncertainty)) Source: bank2_diff_ch_matrix<1><1> (PAD) Destination: AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[1].ADC_channelXX_create_frame/Channel_DDR/iddr_inst (FF) Destination Clock: AD9249_dig_data_interface/DCO_2_BUFG rising at 0.000ns Requirement: 3.000ns Data Path Delay: 4.315ns (Levels of Logic = 1) Clock Path Delay: 3.591ns (Levels of Logic = 2) Clock Uncertainty: 0.025ns Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: bank2_diff_ch_matrix<1><1> to AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[1].ADC_channelXX_create_frame/Channel_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- A10.I Tiopi 1.011 bank2_diff_ch_matrix<1><1> bank2_diff_ch_matrix<1><1> AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[1].ADC_channelXX_create_frame/IB/IBUFDS ILOGIC_X2Y115.DDLY net (fanout=1) 3.191 AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[1].ADC_channelXX_create_frame/ch_in ILOGIC_X2Y115.CLK Tidockd 0.113 AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[1].ADC_channelXX_create_frame/channel_nib<1> AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[1].ADC_channelXX_create_frame/Channel_DDR/iddr_inst ------------------------------------------------- --------------------------- Total 4.315ns (1.124ns logic, 3.191ns route) (26.0% logic, 74.0% route) Minimum Clock Path at Slow Process Corner: DCO2_p to AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[1].ADC_channelXX_create_frame/Channel_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- H11.I Tiopi 0.929 DCO2_p DCO2_p AD9249_dig_data_interface/IB_DCO2/IBUFDS BUFGCTRL_X0Y31.I0 net (fanout=1) 1.091 AD9249_dig_data_interface/DCO_2 BUFGCTRL_X0Y31.O Tbgcko_O 0.074 AD9249_dig_data_interface/DCO_2_BUFG AD9249_dig_data_interface/DCO_2_BUFG ILOGIC_X2Y115.CLK net (fanout=97) 1.497 AD9249_dig_data_interface/DCO_2_BUFG ------------------------------------------------- --------------------------- Total 3.591ns (1.003ns logic, 2.588ns route) (27.9% logic, 72.1% route) -------------------------------------------------------------------------------- Hold Paths: TIMEGRP "din2_timegroup" OFFSET = IN 3 ns VALID 6 ns BEFORE COMP "DCO2_p" "RISING"; -------------------------------------------------------------------------------- Paths for end point AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[2].ADC_channelXX_create_frame/Channel_DDR/iddr_inst (ILOGIC_X2Y111.DDLY), 1 path -------------------------------------------------------------------------------- Slack (hold path): 2.623ns (requirement - (clock path + clock arrival + uncertainty - data path)) Source: bank2_diff_ch_matrix<2><1> (PAD) Destination: AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[2].ADC_channelXX_create_frame/Channel_DDR/iddr_inst (FF) Destination Clock: AD9249_dig_data_interface/DCO_2_BUFG rising at 0.000ns Requirement: 3.000ns Data Path Delay: 1.666ns (Levels of Logic = 1) Clock Path Delay: 2.018ns (Levels of Logic = 2) Clock Uncertainty: 0.025ns Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Minimum Data Path at Fast Process Corner: bank2_diff_ch_matrix<2><1> to AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[2].ADC_channelXX_create_frame/Channel_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- H13.I Tiopi 0.494 bank2_diff_ch_matrix<2><1> bank2_diff_ch_matrix<2><1> AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[2].ADC_channelXX_create_frame/IB/IBUFDS ILOGIC_X2Y111.DDLY net (fanout=1) 1.175 AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[2].ADC_channelXX_create_frame/ch_in ILOGIC_X2Y111.CLK Tiockdd (-Th) 0.003 AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[2].ADC_channelXX_create_frame/channel_nib<1> AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[2].ADC_channelXX_create_frame/Channel_DDR/iddr_inst ------------------------------------------------- --------------------------- Total 1.666ns (0.491ns logic, 1.175ns route) (29.5% logic, 70.5% route) Maximum Clock Path at Fast Process Corner: DCO2_p to AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[2].ADC_channelXX_create_frame/Channel_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- H11.I Tiopi 0.600 DCO2_p DCO2_p AD9249_dig_data_interface/IB_DCO2/IBUFDS BUFGCTRL_X0Y31.I0 net (fanout=1) 0.578 AD9249_dig_data_interface/DCO_2 BUFGCTRL_X0Y31.O Tbgcko_O 0.035 AD9249_dig_data_interface/DCO_2_BUFG AD9249_dig_data_interface/DCO_2_BUFG ILOGIC_X2Y111.CLK net (fanout=97) 0.805 AD9249_dig_data_interface/DCO_2_BUFG ------------------------------------------------- --------------------------- Total 2.018ns (0.635ns logic, 1.383ns route) (31.5% logic, 68.5% route) -------------------------------------------------------------------------------- Paths for end point AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[7].ADC_channelXX_create_frame/Channel_DDR/iddr_inst (ILOGIC_X2Y83.DDLY), 1 path -------------------------------------------------------------------------------- Slack (hold path): 2.636ns (requirement - (clock path + clock arrival + uncertainty - data path)) Source: bank2_diff_ch_matrix<7><1> (PAD) Destination: AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[7].ADC_channelXX_create_frame/Channel_DDR/iddr_inst (FF) Destination Clock: AD9249_dig_data_interface/DCO_2_BUFG rising at 0.000ns Requirement: 3.000ns Data Path Delay: 1.690ns (Levels of Logic = 1) Clock Path Delay: 2.029ns (Levels of Logic = 2) Clock Uncertainty: 0.025ns Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Minimum Data Path at Fast Process Corner: bank2_diff_ch_matrix<7><1> to AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[7].ADC_channelXX_create_frame/Channel_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- K9.I Tiopi 0.518 bank2_diff_ch_matrix<7><1> bank2_diff_ch_matrix<7><1> AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[7].ADC_channelXX_create_frame/IB/IBUFDS ILOGIC_X2Y83.DDLY net (fanout=1) 1.175 AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[7].ADC_channelXX_create_frame/ch_in ILOGIC_X2Y83.CLK Tiockdd (-Th) 0.003 AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[7].ADC_channelXX_create_frame/channel_nib<1> AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[7].ADC_channelXX_create_frame/Channel_DDR/iddr_inst ------------------------------------------------- --------------------------- Total 1.690ns (0.515ns logic, 1.175ns route) (30.5% logic, 69.5% route) Maximum Clock Path at Fast Process Corner: DCO2_p to AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[7].ADC_channelXX_create_frame/Channel_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- H11.I Tiopi 0.600 DCO2_p DCO2_p AD9249_dig_data_interface/IB_DCO2/IBUFDS BUFGCTRL_X0Y31.I0 net (fanout=1) 0.578 AD9249_dig_data_interface/DCO_2 BUFGCTRL_X0Y31.O Tbgcko_O 0.035 AD9249_dig_data_interface/DCO_2_BUFG AD9249_dig_data_interface/DCO_2_BUFG ILOGIC_X2Y83.CLK net (fanout=97) 0.816 AD9249_dig_data_interface/DCO_2_BUFG ------------------------------------------------- --------------------------- Total 2.029ns (0.635ns logic, 1.394ns route) (31.3% logic, 68.7% route) -------------------------------------------------------------------------------- Paths for end point AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[0].ADC_channelXX_create_frame/Channel_DDR/iddr_inst (ILOGIC_X2Y87.DDLY), 1 path -------------------------------------------------------------------------------- Slack (hold path): 2.638ns (requirement - (clock path + clock arrival + uncertainty - data path)) Source: bank2_diff_ch_matrix<0><1> (PAD) Destination: AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[0].ADC_channelXX_create_frame/Channel_DDR/iddr_inst (FF) Destination Clock: AD9249_dig_data_interface/DCO_2_BUFG rising at 0.000ns Requirement: 3.000ns Data Path Delay: 1.681ns (Levels of Logic = 1) Clock Path Delay: 2.018ns (Levels of Logic = 2) Clock Uncertainty: 0.025ns Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Minimum Data Path at Fast Process Corner: bank2_diff_ch_matrix<0><1> to AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[0].ADC_channelXX_create_frame/Channel_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- J11.I Tiopi 0.509 bank2_diff_ch_matrix<0><1> bank2_diff_ch_matrix<0><1> AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[0].ADC_channelXX_create_frame/IB/IBUFDS ILOGIC_X2Y87.DDLY net (fanout=1) 1.175 AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[0].ADC_channelXX_create_frame/ch_in ILOGIC_X2Y87.CLK Tiockdd (-Th) 0.003 AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[0].ADC_channelXX_create_frame/channel_nib<1> AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[0].ADC_channelXX_create_frame/Channel_DDR/iddr_inst ------------------------------------------------- --------------------------- Total 1.681ns (0.506ns logic, 1.175ns route) (30.1% logic, 69.9% route) Maximum Clock Path at Fast Process Corner: DCO2_p to AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[0].ADC_channelXX_create_frame/Channel_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- H11.I Tiopi 0.600 DCO2_p DCO2_p AD9249_dig_data_interface/IB_DCO2/IBUFDS BUFGCTRL_X0Y31.I0 net (fanout=1) 0.578 AD9249_dig_data_interface/DCO_2 BUFGCTRL_X0Y31.O Tbgcko_O 0.035 AD9249_dig_data_interface/DCO_2_BUFG AD9249_dig_data_interface/DCO_2_BUFG ILOGIC_X2Y87.CLK net (fanout=97) 0.805 AD9249_dig_data_interface/DCO_2_BUFG ------------------------------------------------- --------------------------- Total 2.018ns (0.635ns logic, 1.383ns route) (31.5% logic, 68.5% route) -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TIMEGRP "din2_timegroup" OFFSET = IN 3 ns VALID 6 ns BEFORE COMP "DCO2_p" "FALLING"; For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). 9 paths analyzed, 9 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) Minimum allowable offset is 0.764ns. -------------------------------------------------------------------------------- Paths for end point AD9249_dig_data_interface/ADC_bank2/FCO_DDR/iddr_inst (ILOGIC_X2Y95.DDLY), 1 path -------------------------------------------------------------------------------- Slack (setup path): 2.236ns (requirement - (data path - clock path - clock arrival + uncertainty)) Source: FCO2_p (PAD) Destination: AD9249_dig_data_interface/ADC_bank2/FCO_DDR/iddr_inst (FF) Destination Clock: AD9249_dig_data_interface/DCO_2_BUFG falling at 0.000ns Requirement: 3.000ns Data Path Delay: 4.320ns (Levels of Logic = 1) Clock Path Delay: 3.581ns (Levels of Logic = 2) Clock Uncertainty: 0.025ns Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: FCO2_p to AD9249_dig_data_interface/ADC_bank2/FCO_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- B9.I Tiopi 1.014 FCO2_p FCO2_p AD9249_dig_data_interface/IB_FCO2/IBUFDS ILOGIC_X2Y95.DDLY net (fanout=1) 3.191 AD9249_dig_data_interface/FCO_2 ILOGIC_X2Y95.CLKB Tidockd 0.115 AD9249_dig_data_interface/ADC_bank2/fco_data_nib<1> AD9249_dig_data_interface/ADC_bank2/FCO_DDR/iddr_inst ------------------------------------------------- --------------------------- Total 4.320ns (1.129ns logic, 3.191ns route) (26.1% logic, 73.9% route) Minimum Clock Path at Slow Process Corner: DCO2_p to AD9249_dig_data_interface/ADC_bank2/FCO_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- H11.I Tiopi 0.929 DCO2_p DCO2_p AD9249_dig_data_interface/IB_DCO2/IBUFDS BUFGCTRL_X0Y31.I0 net (fanout=1) 1.091 AD9249_dig_data_interface/DCO_2 BUFGCTRL_X0Y31.O Tbgcko_O 0.074 AD9249_dig_data_interface/DCO_2_BUFG AD9249_dig_data_interface/DCO_2_BUFG ILOGIC_X2Y95.CLKB net (fanout=97) 1.487 AD9249_dig_data_interface/DCO_2_BUFG ------------------------------------------------- --------------------------- Total 3.581ns (1.003ns logic, 2.578ns route) (28.0% logic, 72.0% route) -------------------------------------------------------------------------------- Paths for end point AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[4].ADC_channelXX_create_frame/Channel_DDR/iddr_inst (ILOGIC_X2Y91.DDLY), 1 path -------------------------------------------------------------------------------- Slack (setup path): 2.237ns (requirement - (data path - clock path - clock arrival + uncertainty)) Source: bank2_diff_ch_matrix<4><1> (PAD) Destination: AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[4].ADC_channelXX_create_frame/Channel_DDR/iddr_inst (FF) Destination Clock: AD9249_dig_data_interface/DCO_2_BUFG falling at 0.000ns Requirement: 3.000ns Data Path Delay: 4.319ns (Levels of Logic = 1) Clock Path Delay: 3.581ns (Levels of Logic = 2) Clock Uncertainty: 0.025ns Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: bank2_diff_ch_matrix<4><1> to AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[4].ADC_channelXX_create_frame/Channel_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- D7.I Tiopi 1.013 bank2_diff_ch_matrix<4><1> bank2_diff_ch_matrix<4><1> AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[4].ADC_channelXX_create_frame/IB/IBUFDS ILOGIC_X2Y91.DDLY net (fanout=1) 3.191 AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[4].ADC_channelXX_create_frame/ch_in ILOGIC_X2Y91.CLKB Tidockd 0.115 AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[4].ADC_channelXX_create_frame/channel_nib<1> AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[4].ADC_channelXX_create_frame/Channel_DDR/iddr_inst ------------------------------------------------- --------------------------- Total 4.319ns (1.128ns logic, 3.191ns route) (26.1% logic, 73.9% route) Minimum Clock Path at Slow Process Corner: DCO2_p to AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[4].ADC_channelXX_create_frame/Channel_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- H11.I Tiopi 0.929 DCO2_p DCO2_p AD9249_dig_data_interface/IB_DCO2/IBUFDS BUFGCTRL_X0Y31.I0 net (fanout=1) 1.091 AD9249_dig_data_interface/DCO_2 BUFGCTRL_X0Y31.O Tbgcko_O 0.074 AD9249_dig_data_interface/DCO_2_BUFG AD9249_dig_data_interface/DCO_2_BUFG ILOGIC_X2Y91.CLKB net (fanout=97) 1.487 AD9249_dig_data_interface/DCO_2_BUFG ------------------------------------------------- --------------------------- Total 3.581ns (1.003ns logic, 2.578ns route) (28.0% logic, 72.0% route) -------------------------------------------------------------------------------- Paths for end point AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[1].ADC_channelXX_create_frame/Channel_DDR/iddr_inst (ILOGIC_X2Y115.DDLY), 1 path -------------------------------------------------------------------------------- Slack (setup path): 2.249ns (requirement - (data path - clock path - clock arrival + uncertainty)) Source: bank2_diff_ch_matrix<1><1> (PAD) Destination: AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[1].ADC_channelXX_create_frame/Channel_DDR/iddr_inst (FF) Destination Clock: AD9249_dig_data_interface/DCO_2_BUFG falling at 0.000ns Requirement: 3.000ns Data Path Delay: 4.317ns (Levels of Logic = 1) Clock Path Delay: 3.591ns (Levels of Logic = 2) Clock Uncertainty: 0.025ns Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path at Slow Process Corner: bank2_diff_ch_matrix<1><1> to AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[1].ADC_channelXX_create_frame/Channel_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- A10.I Tiopi 1.011 bank2_diff_ch_matrix<1><1> bank2_diff_ch_matrix<1><1> AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[1].ADC_channelXX_create_frame/IB/IBUFDS ILOGIC_X2Y115.DDLY net (fanout=1) 3.191 AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[1].ADC_channelXX_create_frame/ch_in ILOGIC_X2Y115.CLKB Tidockd 0.115 AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[1].ADC_channelXX_create_frame/channel_nib<1> AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[1].ADC_channelXX_create_frame/Channel_DDR/iddr_inst ------------------------------------------------- --------------------------- Total 4.317ns (1.126ns logic, 3.191ns route) (26.1% logic, 73.9% route) Minimum Clock Path at Slow Process Corner: DCO2_p to AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[1].ADC_channelXX_create_frame/Channel_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- H11.I Tiopi 0.929 DCO2_p DCO2_p AD9249_dig_data_interface/IB_DCO2/IBUFDS BUFGCTRL_X0Y31.I0 net (fanout=1) 1.091 AD9249_dig_data_interface/DCO_2 BUFGCTRL_X0Y31.O Tbgcko_O 0.074 AD9249_dig_data_interface/DCO_2_BUFG AD9249_dig_data_interface/DCO_2_BUFG ILOGIC_X2Y115.CLKB net (fanout=97) 1.497 AD9249_dig_data_interface/DCO_2_BUFG ------------------------------------------------- --------------------------- Total 3.591ns (1.003ns logic, 2.588ns route) (27.9% logic, 72.1% route) -------------------------------------------------------------------------------- Hold Paths: TIMEGRP "din2_timegroup" OFFSET = IN 3 ns VALID 6 ns BEFORE COMP "DCO2_p" "FALLING"; -------------------------------------------------------------------------------- Paths for end point AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[2].ADC_channelXX_create_frame/Channel_DDR/iddr_inst (ILOGIC_X2Y111.DDLY), 1 path -------------------------------------------------------------------------------- Slack (hold path): 2.625ns (requirement - (clock path + clock arrival + uncertainty - data path)) Source: bank2_diff_ch_matrix<2><1> (PAD) Destination: AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[2].ADC_channelXX_create_frame/Channel_DDR/iddr_inst (FF) Destination Clock: AD9249_dig_data_interface/DCO_2_BUFG falling at 0.000ns Requirement: 3.000ns Data Path Delay: 1.668ns (Levels of Logic = 1) Clock Path Delay: 2.018ns (Levels of Logic = 2) Clock Uncertainty: 0.025ns Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Minimum Data Path at Fast Process Corner: bank2_diff_ch_matrix<2><1> to AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[2].ADC_channelXX_create_frame/Channel_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- H13.I Tiopi 0.494 bank2_diff_ch_matrix<2><1> bank2_diff_ch_matrix<2><1> AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[2].ADC_channelXX_create_frame/IB/IBUFDS ILOGIC_X2Y111.DDLY net (fanout=1) 1.175 AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[2].ADC_channelXX_create_frame/ch_in ILOGIC_X2Y111.CLKB Tiockdd (-Th) 0.001 AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[2].ADC_channelXX_create_frame/channel_nib<1> AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[2].ADC_channelXX_create_frame/Channel_DDR/iddr_inst ------------------------------------------------- --------------------------- Total 1.668ns (0.493ns logic, 1.175ns route) (29.6% logic, 70.4% route) Maximum Clock Path at Fast Process Corner: DCO2_p to AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[2].ADC_channelXX_create_frame/Channel_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- H11.I Tiopi 0.600 DCO2_p DCO2_p AD9249_dig_data_interface/IB_DCO2/IBUFDS BUFGCTRL_X0Y31.I0 net (fanout=1) 0.578 AD9249_dig_data_interface/DCO_2 BUFGCTRL_X0Y31.O Tbgcko_O 0.035 AD9249_dig_data_interface/DCO_2_BUFG AD9249_dig_data_interface/DCO_2_BUFG ILOGIC_X2Y111.CLKB net (fanout=97) 0.805 AD9249_dig_data_interface/DCO_2_BUFG ------------------------------------------------- --------------------------- Total 2.018ns (0.635ns logic, 1.383ns route) (31.5% logic, 68.5% route) -------------------------------------------------------------------------------- Paths for end point AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[7].ADC_channelXX_create_frame/Channel_DDR/iddr_inst (ILOGIC_X2Y83.DDLY), 1 path -------------------------------------------------------------------------------- Slack (hold path): 2.638ns (requirement - (clock path + clock arrival + uncertainty - data path)) Source: bank2_diff_ch_matrix<7><1> (PAD) Destination: AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[7].ADC_channelXX_create_frame/Channel_DDR/iddr_inst (FF) Destination Clock: AD9249_dig_data_interface/DCO_2_BUFG falling at 0.000ns Requirement: 3.000ns Data Path Delay: 1.692ns (Levels of Logic = 1) Clock Path Delay: 2.029ns (Levels of Logic = 2) Clock Uncertainty: 0.025ns Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Minimum Data Path at Fast Process Corner: bank2_diff_ch_matrix<7><1> to AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[7].ADC_channelXX_create_frame/Channel_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- K9.I Tiopi 0.518 bank2_diff_ch_matrix<7><1> bank2_diff_ch_matrix<7><1> AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[7].ADC_channelXX_create_frame/IB/IBUFDS ILOGIC_X2Y83.DDLY net (fanout=1) 1.175 AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[7].ADC_channelXX_create_frame/ch_in ILOGIC_X2Y83.CLKB Tiockdd (-Th) 0.001 AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[7].ADC_channelXX_create_frame/channel_nib<1> AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[7].ADC_channelXX_create_frame/Channel_DDR/iddr_inst ------------------------------------------------- --------------------------- Total 1.692ns (0.517ns logic, 1.175ns route) (30.6% logic, 69.4% route) Maximum Clock Path at Fast Process Corner: DCO2_p to AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[7].ADC_channelXX_create_frame/Channel_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- H11.I Tiopi 0.600 DCO2_p DCO2_p AD9249_dig_data_interface/IB_DCO2/IBUFDS BUFGCTRL_X0Y31.I0 net (fanout=1) 0.578 AD9249_dig_data_interface/DCO_2 BUFGCTRL_X0Y31.O Tbgcko_O 0.035 AD9249_dig_data_interface/DCO_2_BUFG AD9249_dig_data_interface/DCO_2_BUFG ILOGIC_X2Y83.CLKB net (fanout=97) 0.816 AD9249_dig_data_interface/DCO_2_BUFG ------------------------------------------------- --------------------------- Total 2.029ns (0.635ns logic, 1.394ns route) (31.3% logic, 68.7% route) -------------------------------------------------------------------------------- Paths for end point AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[0].ADC_channelXX_create_frame/Channel_DDR/iddr_inst (ILOGIC_X2Y87.DDLY), 1 path -------------------------------------------------------------------------------- Slack (hold path): 2.640ns (requirement - (clock path + clock arrival + uncertainty - data path)) Source: bank2_diff_ch_matrix<0><1> (PAD) Destination: AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[0].ADC_channelXX_create_frame/Channel_DDR/iddr_inst (FF) Destination Clock: AD9249_dig_data_interface/DCO_2_BUFG falling at 0.000ns Requirement: 3.000ns Data Path Delay: 1.683ns (Levels of Logic = 1) Clock Path Delay: 2.018ns (Levels of Logic = 2) Clock Uncertainty: 0.025ns Clock Uncertainty: 0.025ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.050ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Minimum Data Path at Fast Process Corner: bank2_diff_ch_matrix<0><1> to AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[0].ADC_channelXX_create_frame/Channel_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- J11.I Tiopi 0.509 bank2_diff_ch_matrix<0><1> bank2_diff_ch_matrix<0><1> AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[0].ADC_channelXX_create_frame/IB/IBUFDS ILOGIC_X2Y87.DDLY net (fanout=1) 1.175 AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[0].ADC_channelXX_create_frame/ch_in ILOGIC_X2Y87.CLKB Tiockdd (-Th) 0.001 AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[0].ADC_channelXX_create_frame/channel_nib<1> AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[0].ADC_channelXX_create_frame/Channel_DDR/iddr_inst ------------------------------------------------- --------------------------- Total 1.683ns (0.508ns logic, 1.175ns route) (30.2% logic, 69.8% route) Maximum Clock Path at Fast Process Corner: DCO2_p to AD9249_dig_data_interface/ADC_bank2/generate_channel_bank[0].ADC_channelXX_create_frame/Channel_DDR/iddr_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- H11.I Tiopi 0.600 DCO2_p DCO2_p AD9249_dig_data_interface/IB_DCO2/IBUFDS BUFGCTRL_X0Y31.I0 net (fanout=1) 0.578 AD9249_dig_data_interface/DCO_2 BUFGCTRL_X0Y31.O Tbgcko_O 0.035 AD9249_dig_data_interface/DCO_2_BUFG AD9249_dig_data_interface/DCO_2_BUFG ILOGIC_X2Y87.CLKB net (fanout=97) 0.805 AD9249_dig_data_interface/DCO_2_BUFG ------------------------------------------------- --------------------------- Total 2.018ns (0.635ns logic, 1.383ns route) (31.5% logic, 68.5% route) -------------------------------------------------------------------------------- Derived Constraint Report Derived Constraints for TS_evb_ref_clk_p +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ | | Period | Actual Period | Timing Errors | Paths Analyzed | | Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| | | | Direct | Derivative | Direct | Derivative | Direct | Derivative | +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ |TS_evb_ref_clk_p | 10.000ns| 4.000ns| 4.685ns| 0| 0| 0| 8598| | TS_System_clk_management_spi_2| 100.000ns| 30.200ns| N/A| 0| 0| 615| 0| | x_sclk | | | | | | | | | TS_System_clk_management_sys_c| 10.000ns| 4.685ns| N/A| 0| 0| 7983| 0| | lk | | | | | | | | +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ All constraints were met. Data Sheet report: ----------------- All values displayed in nanoseconds (ns) Setup/Hold to clock DCO1_p --------------------------+------------+------------+------------+------------+------------------------------------+--------+ |Max Setup to| Process |Max Hold to | Process | | Clock | Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase | --------------------------+------------+------------+------------+------------+------------------------------------+--------+ FCO1_p | -0.553(R)| FAST | 2.323(R)| SLOW |AD9249_dig_data_interface/DCO_1_BUFG| 0.000| | -0.552(F)| FAST | 2.321(F)| SLOW |AD9249_dig_data_interface/DCO_1_BUFG| 0.000| bank1_diff_ch_matrix<0><1>| -0.600(R)| FAST | 2.361(R)| SLOW |AD9249_dig_data_interface/DCO_1_BUFG| 0.000| | -0.599(F)| FAST | 2.359(F)| SLOW |AD9249_dig_data_interface/DCO_1_BUFG| 0.000| bank1_diff_ch_matrix<1><1>| -0.597(R)| FAST | 2.361(R)| SLOW |AD9249_dig_data_interface/DCO_1_BUFG| 0.000| | -0.596(F)| FAST | 2.359(F)| SLOW |AD9249_dig_data_interface/DCO_1_BUFG| 0.000| bank1_diff_ch_matrix<2><1>| -0.542(R)| FAST | 2.323(R)| SLOW |AD9249_dig_data_interface/DCO_1_BUFG| 0.000| | -0.541(F)| FAST | 2.321(F)| SLOW |AD9249_dig_data_interface/DCO_1_BUFG| 0.000| bank1_diff_ch_matrix<3><1>| -0.592(R)| FAST | 2.354(R)| SLOW |AD9249_dig_data_interface/DCO_1_BUFG| 0.000| | -0.591(F)| FAST | 2.352(F)| SLOW |AD9249_dig_data_interface/DCO_1_BUFG| 0.000| bank1_diff_ch_matrix<4><1>| -0.563(R)| FAST | 2.329(R)| SLOW |AD9249_dig_data_interface/DCO_1_BUFG| 0.000| | -0.562(F)| FAST | 2.327(F)| SLOW |AD9249_dig_data_interface/DCO_1_BUFG| 0.000| bank1_diff_ch_matrix<5><1>| -0.563(R)| FAST | 2.340(R)| SLOW |AD9249_dig_data_interface/DCO_1_BUFG| 0.000| | -0.562(F)| FAST | 2.338(F)| SLOW |AD9249_dig_data_interface/DCO_1_BUFG| 0.000| bank1_diff_ch_matrix<6><1>| -0.565(R)| FAST | 2.331(R)| SLOW |AD9249_dig_data_interface/DCO_1_BUFG| 0.000| | -0.564(F)| FAST | 2.329(F)| SLOW |AD9249_dig_data_interface/DCO_1_BUFG| 0.000| bank1_diff_ch_matrix<7><1>| -0.579(R)| FAST | 2.345(R)| SLOW |AD9249_dig_data_interface/DCO_1_BUFG| 0.000| | -0.578(F)| FAST | 2.343(F)| SLOW |AD9249_dig_data_interface/DCO_1_BUFG| 0.000| --------------------------+------------+------------+------------+------------+------------------------------------+--------+ Setup/Hold to clock DCO2_p --------------------------+------------+------------+------------+------------+------------------------------------+--------+ |Max Setup to| Process |Max Hold to | Process | | Clock | Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase | --------------------------+------------+------------+------------+------------+------------------------------------+--------+ FCO2_p | 0.762(R)| SLOW | 0.323(R)| FAST |AD9249_dig_data_interface/DCO_2_BUFG| 0.000| | 0.764(F)| SLOW | 0.321(F)| FAST |AD9249_dig_data_interface/DCO_2_BUFG| 0.000| bank2_diff_ch_matrix<0><1>| 0.707(R)| SLOW | 0.362(R)| FAST |AD9249_dig_data_interface/DCO_2_BUFG| 0.000| | 0.709(F)| SLOW | 0.360(F)| FAST |AD9249_dig_data_interface/DCO_2_BUFG| 0.000| bank2_diff_ch_matrix<1><1>| 0.749(R)| SLOW | 0.326(R)| FAST |AD9249_dig_data_interface/DCO_2_BUFG| 0.000| | 0.751(F)| SLOW | 0.324(F)| FAST |AD9249_dig_data_interface/DCO_2_BUFG| 0.000| bank2_diff_ch_matrix<2><1>| 0.689(R)| SLOW | 0.377(R)| FAST |AD9249_dig_data_interface/DCO_2_BUFG| 0.000| | 0.691(F)| SLOW | 0.375(F)| FAST |AD9249_dig_data_interface/DCO_2_BUFG| 0.000| bank2_diff_ch_matrix<3><1>| 0.744(R)| SLOW | 0.338(R)| FAST |AD9249_dig_data_interface/DCO_2_BUFG| 0.000| | 0.746(F)| SLOW | 0.336(F)| FAST |AD9249_dig_data_interface/DCO_2_BUFG| 0.000| bank2_diff_ch_matrix<4><1>| 0.761(R)| SLOW | 0.324(R)| FAST |AD9249_dig_data_interface/DCO_2_BUFG| 0.000| | 0.763(F)| SLOW | 0.322(F)| FAST |AD9249_dig_data_interface/DCO_2_BUFG| 0.000| bank2_diff_ch_matrix<5><1>| 0.747(R)| SLOW | 0.336(R)| FAST |AD9249_dig_data_interface/DCO_2_BUFG| 0.000| | 0.749(F)| SLOW | 0.334(F)| FAST |AD9249_dig_data_interface/DCO_2_BUFG| 0.000| bank2_diff_ch_matrix<6><1>| 0.730(R)| SLOW | 0.342(R)| FAST |AD9249_dig_data_interface/DCO_2_BUFG| 0.000| | 0.732(F)| SLOW | 0.340(F)| FAST |AD9249_dig_data_interface/DCO_2_BUFG| 0.000| bank2_diff_ch_matrix<7><1>| 0.716(R)| SLOW | 0.364(R)| FAST |AD9249_dig_data_interface/DCO_2_BUFG| 0.000| | 0.718(F)| SLOW | 0.362(F)| FAST |AD9249_dig_data_interface/DCO_2_BUFG| 0.000| --------------------------+------------+------------+------------+------------+------------------------------------+--------+ Clock to Setup on destination clock DCO1_n ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ DCO1_n | 3.915| | | | DCO1_p | 3.915| | | | ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock DCO1_p ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ DCO1_n | 3.915| | | | DCO1_p | 3.915| | | | ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock DCO2_n ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ DCO2_n | 4.191| | | | DCO2_p | 4.191| | | | ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock DCO2_p ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ DCO2_n | 4.191| | | | DCO2_p | 4.191| | | | ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock evb_ref_clk_n ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ evb_ref_clk_n | 4.685| | | | evb_ref_clk_p | 4.685| | | | ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock evb_ref_clk_p ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ evb_ref_clk_n | 4.685| | | | evb_ref_clk_p | 4.685| | | | ---------------+---------+---------+---------+---------+ TIMEGRP "din1_timegroup" OFFSET = IN 3 ns VALID 6 ns BEFORE COMP "DCO1_p" "RISING"; Worst Case Data Window 1.819; Ideal Clock Offset To Actual Clock -1.451; --------------------------+------------+------------+------------+------------+---------+---------+-------------+ | | Process | | Process | Setup | Hold |Source Offset| Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | --------------------------+------------+------------+------------+------------+---------+---------+-------------+ FCO1_p | -0.553(R)| FAST | 2.323(R)| SLOW | 3.553| 0.677| 1.438| bank1_diff_ch_matrix<0><1>| -0.600(R)| FAST | 2.361(R)| SLOW | 3.600| 0.639| 1.481| bank1_diff_ch_matrix<1><1>| -0.597(R)| FAST | 2.361(R)| SLOW | 3.597| 0.639| 1.479| bank1_diff_ch_matrix<2><1>| -0.542(R)| FAST | 2.323(R)| SLOW | 3.542| 0.677| 1.432| bank1_diff_ch_matrix<3><1>| -0.592(R)| FAST | 2.354(R)| SLOW | 3.592| 0.646| 1.473| bank1_diff_ch_matrix<4><1>| -0.563(R)| FAST | 2.329(R)| SLOW | 3.563| 0.671| 1.446| bank1_diff_ch_matrix<5><1>| -0.563(R)| FAST | 2.340(R)| SLOW | 3.563| 0.660| 1.452| bank1_diff_ch_matrix<6><1>| -0.565(R)| FAST | 2.331(R)| SLOW | 3.565| 0.669| 1.448| bank1_diff_ch_matrix<7><1>| -0.579(R)| FAST | 2.345(R)| SLOW | 3.579| 0.655| 1.462| --------------------------+------------+------------+------------+------------+---------+---------+-------------+ Worst Case Summary | -0.542| - | 2.361| - | 3.542| 0.639| | --------------------------+------------+------------+------------+------------+---------+---------+-------------+ TIMEGRP "din1_timegroup" OFFSET = IN 3 ns VALID 6 ns BEFORE COMP "DCO1_p" "FALLING"; Worst Case Data Window 14.600; Ideal Clock Offset To Actual Clock -1.450; --------------------------+------------+------------+------------+------------+---------+---------+-------------+ | | Process | | Process | Setup | Hold |Source Offset| Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | --------------------------+------------+------------+------------+------------+---------+---------+-------------+ FCO1_p | -15.936(F)| FAST | 17.705(F)| SLOW | 3.552| 0.679| 1.437| bank1_diff_ch_matrix<0><1>| -3.163(F)| FAST | 4.923(F)| SLOW | 3.599| 0.641| 1.479| bank1_diff_ch_matrix<1><1>| -3.160(F)| FAST | 4.923(F)| SLOW | 3.596| 0.641| 1.478| bank1_diff_ch_matrix<2><1>| -3.105(F)| FAST | 4.885(F)| SLOW | 3.541| 0.679| 1.431| bank1_diff_ch_matrix<3><1>| -3.155(F)| FAST | 4.916(F)| SLOW | 3.591| 0.648| 1.472| bank1_diff_ch_matrix<4><1>| -3.126(F)| FAST | 4.891(F)| SLOW | 3.562| 0.673| 1.444| bank1_diff_ch_matrix<5><1>| -3.126(F)| FAST | 4.902(F)| SLOW | 3.562| 0.662| 1.450| bank1_diff_ch_matrix<6><1>| -3.128(F)| FAST | 4.893(F)| SLOW | 3.564| 0.671| 1.446| bank1_diff_ch_matrix<7><1>| -3.142(F)| FAST | 4.907(F)| SLOW | 3.578| 0.657| 1.461| --------------------------+------------+------------+------------+------------+---------+---------+-------------+ Worst Case Summary | -3.105| - | 17.705| - | 3.541| 0.641| | --------------------------+------------+------------+------------+------------+---------+---------+-------------+ TIMEGRP "din2_timegroup" OFFSET = IN 3 ns VALID 6 ns BEFORE COMP "DCO2_p" "RISING"; Worst Case Data Window 1.139; Ideal Clock Offset To Actual Clock 0.193; --------------------------+------------+------------+------------+------------+---------+---------+-------------+ | | Process | | Process | Setup | Hold |Source Offset| Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | --------------------------+------------+------------+------------+------------+---------+---------+-------------+ FCO2_p | 0.762(R)| SLOW | 0.323(R)| FAST | 2.238| 2.677| -0.220| bank2_diff_ch_matrix<0><1>| 0.707(R)| SLOW | 0.362(R)| FAST | 2.293| 2.638| -0.172| bank2_diff_ch_matrix<1><1>| 0.749(R)| SLOW | 0.326(R)| FAST | 2.251| 2.674| -0.212| bank2_diff_ch_matrix<2><1>| 0.689(R)| SLOW | 0.377(R)| FAST | 2.311| 2.623| -0.156| bank2_diff_ch_matrix<3><1>| 0.744(R)| SLOW | 0.338(R)| FAST | 2.256| 2.662| -0.203| bank2_diff_ch_matrix<4><1>| 0.761(R)| SLOW | 0.324(R)| FAST | 2.239| 2.676| -0.219| bank2_diff_ch_matrix<5><1>| 0.747(R)| SLOW | 0.336(R)| FAST | 2.253| 2.664| -0.206| bank2_diff_ch_matrix<6><1>| 0.730(R)| SLOW | 0.342(R)| FAST | 2.270| 2.658| -0.194| bank2_diff_ch_matrix<7><1>| 0.716(R)| SLOW | 0.364(R)| FAST | 2.284| 2.636| -0.176| --------------------------+------------+------------+------------+------------+---------+---------+-------------+ Worst Case Summary | 0.762| - | 0.377| - | 2.238| 2.623| | --------------------------+------------+------------+------------+------------+---------+---------+-------------+ TIMEGRP "din2_timegroup" OFFSET = IN 3 ns VALID 6 ns BEFORE COMP "DCO2_p" "FALLING"; Worst Case Data Window 13.904; Ideal Clock Offset To Actual Clock 0.194; --------------------------+------------+------------+------------+------------+---------+---------+-------------+ | | Process | | Process | Setup | Hold |Source Offset| Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | --------------------------+------------+------------+------------+------------+---------+---------+-------------+ FCO2_p | -14.620(F)| SLOW | 15.705(F)| FAST | 2.236| 2.679| -0.221| bank2_diff_ch_matrix<0><1>| -1.855(F)| SLOW | 2.924(F)| FAST | 2.291| 2.640| -0.175| bank2_diff_ch_matrix<1><1>| -1.813(F)| SLOW | 2.888(F)| FAST | 2.249| 2.676| -0.214| bank2_diff_ch_matrix<2><1>| -1.873(F)| SLOW | 2.939(F)| FAST | 2.309| 2.625| -0.158| bank2_diff_ch_matrix<3><1>| -1.818(F)| SLOW | 2.900(F)| FAST | 2.254| 2.664| -0.205| bank2_diff_ch_matrix<4><1>| -1.801(F)| SLOW | 2.886(F)| FAST | 2.237| 2.678| -0.220| bank2_diff_ch_matrix<5><1>| -1.815(F)| SLOW | 2.898(F)| FAST | 2.251| 2.666| -0.208| bank2_diff_ch_matrix<6><1>| -1.832(F)| SLOW | 2.904(F)| FAST | 2.268| 2.660| -0.196| bank2_diff_ch_matrix<7><1>| -1.846(F)| SLOW | 2.926(F)| FAST | 2.282| 2.638| -0.178| --------------------------+------------+------------+------------+------------+---------+---------+-------------+ Worst Case Summary | -1.801| - | 15.705| - | 2.236| 2.625| | --------------------------+------------+------------+------------+------------+---------+---------+-------------+ Timing summary: --------------- Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0) Constraints cover 11586 paths, 0 nets, and 9236 connections Design statistics: Minimum period: 30.200ns{1} (Maximum frequency: 33.113MHz) Minimum input required time before clock: 0.764ns ------------------------------------Footnotes----------------------------------- 1) The minimum period statistic assumes all single cycle delays. Analysis completed Wed Dec 17 11:20:41 2014 -------------------------------------------------------------------------------- Trace Settings: ------------------------- Trace Settings Peak Memory Usage: 484 MB