##################################################################################
# Period Constraints
##################################################################################
NET "evb_ref_clk_p" TNM_NET = evb_ref_clk_p;
TIMESPEC TS_evb_ref_clk_p = PERIOD "evb_ref_clk_p" 100 MHz LOW 50%;

NET "DCO1_p" TNM_NET = DCO1_p ;
TIMESPEC TS_DCO1_p = PERIOD "DCO1_p" 195 MHz HIGH 50%;
NET "DCO1_n" TNM_NET = DCO1_n ;
TIMESPEC TS_DCO1_n = PERIOD "DCO1_n" 195 MHz HIGH 50%;

NET "DCO2_p" TNM_NET = DCO2_p ;
TIMESPEC TS_DCO2_p = PERIOD "DCO2_p" 195 MHz HIGH 50%;
NET "DCO2_n" TNM_NET = DCO2_n ;
TIMESPEC TS_DCO2_n = PERIOD "DCO2_n" 195 MHz HIGH 50%;

NET FCO1_p TNM_NET = FCO1_p ;
TIMESPEC TS_FCO1_p = PERIOD "FCO1_p" 32.5 MHz HIGH 50%;

NET FCO2_p TNM_NET = FCO2_p ;
TIMESPEC TS_FCO2_p = PERIOD "FCO2_p" 32.5 MHz HIGH 50%;	
 
###################################################
# Input Constraints - OFFSET IN
###################################################

NET "FCO1_p" TNM = din1_timegroup;

INST "bank1_diff_ch_matrix<0><1>" TNM = din1_timegroup;
INST "bank1_diff_ch_matrix<1><1>" TNM = din1_timegroup;
INST "bank1_diff_ch_matrix<2><1>" TNM = din1_timegroup;
INST "bank1_diff_ch_matrix<3><1>" TNM = din1_timegroup;
INST "bank1_diff_ch_matrix<4><1>" TNM = din1_timegroup;
INST "bank1_diff_ch_matrix<5><1>" TNM = din1_timegroup;
INST "bank1_diff_ch_matrix<6><1>" TNM = din1_timegroup;
INST "bank1_diff_ch_matrix<7><1>" TNM = din1_timegroup;

TIMEGRP din1_timegroup OFFSET = IN 1ns VALID 2ns BEFORE "DCO1_p" RISING ;
TIMEGRP din1_timegroup OFFSET = IN 1ns VALID 2ns BEFORE "DCO1_p" FALLING ;

NET "FCO2_p" TNM = din2_timegroup;

INST "bank2_diff_ch_matrix<0><1>" TNM = din2_timegroup;
INST "bank2_diff_ch_matrix<1><1>" TNM = din2_timegroup;
INST "bank2_diff_ch_matrix<2><1>" TNM = din2_timegroup;
INST "bank2_diff_ch_matrix<3><1>" TNM = din2_timegroup;
INST "bank2_diff_ch_matrix<4><1>" TNM = din2_timegroup;
INST "bank2_diff_ch_matrix<5><1>" TNM = din2_timegroup;
INST "bank2_diff_ch_matrix<6><1>" TNM = din2_timegroup;
INST "bank2_diff_ch_matrix<7><1>" TNM = din2_timegroup;

TIMEGRP din2_timegroup OFFSET = IN 1ns VALID 2ns BEFORE "DCO2_p" RISING ;
TIMEGRP din2_timegroup OFFSET = IN 1ns VALID 2ns BEFORE "DCO2_p" FALLING ;

##################################################################################
# Reference clock 100MHz
##################################################################################
NET evb_ref_clk_p  LOC = "AD28" |IOSTANDARD = LVDS_25 |DIFF_TERM = TRUE ;

NET evb_ref_clk_n  LOC = "AD27" |IOSTANDARD = LVDS_25 |DIFF_TERM = TRUE ; 

NET BTN_RESET   	LOC = "AE17"  |IOSTANDARD = "SSTL15"  |TIG;  	# PB1
NET LED_1 			LOC = "AE24" 	|IOSTANDARD = LVCMOS25 ; 		#LED1
##################################################################################
# J2
##################################################################################
# Data clock bank 1 and bank 2
##################################################################################
NET DCO1_p   	LOC = "F7"  |DIFF_TERM = "TRUE"  |IOSTANDARD = "LVDS_25";
NET DCO1_n   	LOC = "G7"  |DIFF_TERM = "TRUE"  |IOSTANDARD = "LVDS_25";

NET DCO2_p  	LOC = "H11"  |DIFF_TERM = "TRUE"  |IOSTANDARD = "LVDS_25";
NET DCO2_n   	LOC = "H10"  |DIFF_TERM = "TRUE"  |IOSTANDARD = "LVDS_25";

##################################################################################
# Frame clock bank 1 and bank 2
##################################################################################
NET FCO1_p   	LOC = "B8"  |DIFF_TERM = "TRUE"  |IOSTANDARD = "LVDS_25"	|CLOCK_DEDICATED_ROUTE = FALSE;
NET FCO1_n   	LOC = "C8"  |DIFF_TERM = "TRUE"  |IOSTANDARD = "LVDS_25"	|CLOCK_DEDICATED_ROUTE = FALSE;

NET FCO2_p   	LOC = "B9"  |DIFF_TERM = "TRUE"  |IOSTANDARD = "LVDS_25"	|CLOCK_DEDICATED_ROUTE = FALSE;
NET FCO2_n   	LOC = "C9"  |DIFF_TERM = "TRUE"  |IOSTANDARD = "LVDS_25"	|CLOCK_DEDICATED_ROUTE = FALSE;

##################################################################################
# Digital data port bank 1
##################################################################################
NET bank1_diff_ch_matrix<0><1>		LOC = "J12" |IOSTANDARD = "LVDS_25"	|DIFF_TERM = TRUE; 	#A1_p
NET bank1_diff_ch_matrix<0><0>		LOC = "K13" |IOSTANDARD = "LVDS_25"	|DIFF_TERM = TRUE;	#A1_n
NET bank1_diff_ch_matrix<1><1>		LOC = "F11" |IOSTANDARD = "LVDS_25"	|DIFF_TERM = TRUE;	#B1_p
NET bank1_diff_ch_matrix<1><0>		LOC = "E10" |IOSTANDARD = "LVDS_25"	|DIFF_TERM = TRUE;	#B1_n
NET bank1_diff_ch_matrix<2><1>		LOC = "A7" |IOSTANDARD = "LVDS_25"	|DIFF_TERM = TRUE;	#C1_p
NET bank1_diff_ch_matrix<2><0>		LOC = "B7" |IOSTANDARD = "LVDS_25"	|DIFF_TERM = TRUE;	#C1_n
NET bank1_diff_ch_matrix<3><1>		LOC = "G11" |IOSTANDARD = "LVDS_25"	|DIFF_TERM = TRUE;	#D1_p
NET bank1_diff_ch_matrix<3><0>		LOC = "F10" |IOSTANDARD = "LVDS_25"	|DIFF_TERM = TRUE;	#D1_n
NET bank1_diff_ch_matrix<4><1>		LOC = "E8" |IOSTANDARD = "LVDS_25"	|DIFF_TERM = TRUE;	#E1_p
NET bank1_diff_ch_matrix<4><0>		LOC = "F9" |IOSTANDARD = "LVDS_25"	|DIFF_TERM = TRUE;	#E1_n
NET bank1_diff_ch_matrix<5><1>		LOC = "J7" |IOSTANDARD = "LVDS_25"	|DIFF_TERM = TRUE;	#F1_p
NET bank1_diff_ch_matrix<5><0>		LOC = "J8" |IOSTANDARD = "LVDS_25"	|DIFF_TERM = TRUE;	#F1_n
NET bank1_diff_ch_matrix<6><1>		LOC = "G8" |IOSTANDARD = "LVDS_25"	|DIFF_TERM = TRUE;	#G1_p
NET bank1_diff_ch_matrix<6><0>		LOC = "G9" |IOSTANDARD = "LVDS_25"	|DIFF_TERM = TRUE;	#G1_n
NET bank1_diff_ch_matrix<7><1>		LOC = "K7" |IOSTANDARD = "LVDS_25"	|DIFF_TERM = TRUE;	#H1_p
NET bank1_diff_ch_matrix<7><0>		LOC = "L7" |IOSTANDARD = "LVDS_25"	|DIFF_TERM = TRUE;	#H1_n
##################################################################################
# Digital data port bank 2
##################################################################################
NET bank2_diff_ch_matrix<0><1>		LOC = "J11" |IOSTANDARD = "LVDS_25"	|DIFF_TERM = TRUE;	#A2_p
NET bank2_diff_ch_matrix<0><0>		LOC = "J10" |IOSTANDARD = "LVDS_25"	|DIFF_TERM = TRUE;	#A2_n
NET bank2_diff_ch_matrix<1><1>		LOC = "A10" |IOSTANDARD = "LVDS_25"	|DIFF_TERM = TRUE;	#B2_p
NET bank2_diff_ch_matrix<1><0>		LOC = "A9" |IOSTANDARD = "LVDS_25"	|DIFF_TERM = TRUE;	#B2_n
NET bank2_diff_ch_matrix<2><1>		LOC = "H13" |IOSTANDARD = "LVDS_25"	|DIFF_TERM = TRUE;	#C2_p
NET bank2_diff_ch_matrix<2><0>		LOC = "J13" |IOSTANDARD = "LVDS_25"	|DIFF_TERM = TRUE;	#C2_n
NET bank2_diff_ch_matrix<3><1>		LOC = "D10" |IOSTANDARD = "LVDS_25"	|DIFF_TERM = TRUE;	#D2_p
NET bank2_diff_ch_matrix<3><0>		LOC = "C10" |IOSTANDARD = "LVDS_25"	|DIFF_TERM = TRUE;	#D2_n
NET bank2_diff_ch_matrix<4><1>		LOC = "D7" |IOSTANDARD = "LVDS_25"	|DIFF_TERM = TRUE;	#E2_p
NET bank2_diff_ch_matrix<4><0>		LOC = "E7" |IOSTANDARD = "LVDS_25"	|DIFF_TERM = TRUE;	#E2_n
NET bank2_diff_ch_matrix<5><1>		LOC = "D8" |IOSTANDARD = "LVDS_25"	|DIFF_TERM = TRUE;	#F2_p
NET bank2_diff_ch_matrix<5><0>		LOC = "E9" |IOSTANDARD = "LVDS_25"	|DIFF_TERM = TRUE;	#F2_n
NET bank2_diff_ch_matrix<6><1>		LOC = "H8" |IOSTANDARD = "LVDS_25"	|DIFF_TERM = TRUE;	#G2_p
NET bank2_diff_ch_matrix<6><0>		LOC = "H9" |IOSTANDARD = "LVDS_25"	|DIFF_TERM = TRUE;	#G2_n
NET bank2_diff_ch_matrix<7><1>		LOC = "K9" |IOSTANDARD = "LVDS_25"	|DIFF_TERM = TRUE;	#H2_p
NET bank2_diff_ch_matrix<7><0>		LOC = "K10" |IOSTANDARD = "LVDS_25"	|DIFF_TERM = TRUE;	#H2_p
##################################################################################
# J1
##################################################################################
# SPI interface
##################################################################################
NET spi_sclk      LOC = AB12 |IOSTANDARD = LVCMOS18 ; 

NET spi_sdio     LOC = W12  |IOSTANDARD = LVCMOS18 ;

NET spi_csb1     LOC = AB13 |IOSTANDARD = LVCMOS18 ;

NET spi_csb2     LOC = AA14 |IOSTANDARD = LVCMOS18 ;

###################################################
# Bank IO Supply Control
#
# 00 = 1.2V
# 01 = 1.8V
# 10 = 2.5V
# 11 = not allowed
#
###################################################
NET vadj_b34_sel0    LOC = L24 |IOSTANDARD = LVCMOS18 ; # IO Bank 34 
NET vadj_b34_sel1    LOC = L25 |IOSTANDARD = LVCMOS18 ;
 
NET vadj_b35_sel0    LOC = N28 |IOSTANDARD = LVCMOS18 ; # IO Bank 35
NET vadj_b35_sel1    LOC = M28 |IOSTANDARD = LVCMOS18 ; 

NET vadj_bus_a_sel0  LOC = P26 |IOSTANDARD = LVCMOS18 ; # Parallel data bus A, J2
NET vadj_bus_a_sel1  LOC = P25 |IOSTANDARD = LVCMOS18 ; 

NET vadj_bus_b_sel0  LOC = N20 |IOSTANDARD = LVCMOS18 ; # Parallel data bus B, J3
NET vadj_bus_b_sel1  LOC = N21 |IOSTANDARD = LVCMOS18 ; 


###################################################
# Debug Interface
###################################################
NET debug_header<0>  LOC = Y9   |IOSTANDARD = LVCMOS25 ; # IOSTANDARD must match Bank 35 IO Supply Setting
NET debug_header<1>  LOC = Y10  |IOSTANDARD = LVCMOS25 ;
NET debug_header<2>  LOC = AA10 |IOSTANDARD = LVCMOS25 ;
NET debug_header<3>  LOC = AB9  |IOSTANDARD = LVCMOS25 ;
NET debug_header<4>  LOC = AC10 |IOSTANDARD = LVCMOS25 ;
NET debug_header<5>  LOC = AC9  |IOSTANDARD = LVCMOS25 ;
NET debug_header<6>  LOC = AD8  |IOSTANDARD = LVCMOS25;
NET debug_header<7>  LOC = AF12 |IOSTANDARD = LVCMOS25 ;
NET debug_header<8>  LOC = AE9  |IOSTANDARD = LVCMOS25 ;
NET debug_header<9>  LOC = AF9  |IOSTANDARD = LVCMOS25 ;
NET debug_header<10> LOC = AE8  |IOSTANDARD = LVCMOS25 ;
NET debug_header<11> LOC = AG9  |IOSTANDARD = LVCMOS25 ;
NET debug_header<12> LOC = AH8  |IOSTANDARD = LVCMOS25 ;
NET debug_header<13> LOC = AF7  |IOSTANDARD = LVCMOS25 ;
NET debug_header<14> LOC = AB7  |IOSTANDARD = LVCMOS25 ;
NET debug_header<15> LOC = AA7  |IOSTANDARD = LVCMOS25 ;
NET debug_header<16> LOC = AA9  |IOSTANDARD = LVCMOS25 ;
NET debug_header<17> LOC = W8   |IOSTANDARD = LVCMOS25 ;

NET debug_h1_20  		LOC = AF11 |IOSTANDARD = LVCMOS25 ; # IOSTANDARD must match Bank 35 IO Supply Setting
NET debug_h2_20  		LOC = AF10 |IOSTANDARD = LVCMOS25 ;