(Info) ********************************************************************************************
(Info) Deeds VHDL converter (ver. 1.80.100) is running...
(Info) Convertion started (7:32:34 PM, 12/21/2014) on file:
(Info) --> "Z:\home\cfo\Downloads\Deeds\110043\110043_Byte_Generator_On_FPGA\ByteGenerator.pbs"
(Info) --------------------------------------------------------------------------------------------
(Info) Converting schematic (file: "ByteGenerator.pbs") into VHDL
(Info) Extracting and Coding VHDL components
(Info) VHDL DMC8 CPU transcripted (file: "DMC8.vhd", 109955 bytes)
(Info) VHDL DMC8 Micro Computer description coded (file: "Microcomputer_Module.vhd", 24478 bytes)
(Info) Processing Input and Output Signals
(Warning) Input "!Reset" [Id#2] renamed to "inReset"
(Warning) Input "Microcomputer Module" [Id#164] renamed to "Microcomputer_Module"
(Warning) Input "!Down" [Id#165] renamed to "inDown"
(Warning) Input "!Up" [Id#166] renamed to "inUp"
(Warning) Output "BYTE (hex)" [Id#112] renamed to "oBYTE_hexu"
(Warning) Output "BYTE (bin)" [Id#114] renamed to "oBYTE_binu"
(Warning) Output " Error" [Id#167] renamed to "oError"
(Info) 4 Native Input(s), 3 Native Output(s) processed.
(Info) 0 Added Input(s), 0 Added Output(s), 0 Default Output(s).
(Info) Top level structural VHDL description coded (file "ByteGenerator.vhd", 10846 bytes)
(Info) --------------------------------------------------------------------------------------------
(Info) Saving all the VHDL files in the subfolder:
(Info) --> "Z:\home\cfo\Downloads\Deeds\110043\110043_Byte_Generator_On_FPGA\ByteGenerator_VHDL"
(Info)   |--- "DMC8.vhd" file saved.
(Info)   |--- "Microcomputer_Module.vhd" file saved.
(Info)   |--- "ByteGenerator.vhd" file saved.
(Info) --------------------------------------------------------------------------------------------
(Info) --------------------------------------------------------------------------------------------
(Info) This message list saved on file:
(Info) --> "Z:\home\cfo\Downloads\Deeds\110043\110043_Byte_Generator_On_FPGA\ByteGenerator_VHDL\ReportMessages.txt"
(Info) --------------------------------------------------------------------------------------------
(Info) All files saved! VHDL conversion ended (7:32:42 PM, 12/21/2014)
(Info) ********************************************************************************************
