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/opentcp/arch/mb90f553a/init.c

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00001 /*
00002  *Copyright (c) 2000-2002 Viola Systems Ltd.
00003  *All rights reserved.
00004  *
00005  *Redistribution and use in source and binary forms, with or without 
00006  *modification, are permitted provided that the following conditions 
00007  *are met:
00008  *
00009  *1. Redistributions of source code must retain the above copyright 
00010  *notice, this list of conditions and the following disclaimer.
00011  *
00012  *2. Redistributions in binary form must reproduce the above copyright 
00013  *notice, this list of conditions and the following disclaimer in the 
00014  *documentation and/or other materials provided with the distribution.
00015  *
00016  *3. The end-user documentation included with the redistribution, if 
00017  *any, must include the following acknowledgment:
00018  *      "This product includes software developed by Viola 
00019  *      Systems (http://www.violasystems.com/)."
00020  *
00021  *Alternately, this acknowledgment may appear in the software itself, 
00022  *if and wherever such third-party acknowledgments normally appear.
00023  *
00024  *4. The names "OpenTCP" and "Viola Systems" must not be used to 
00025  *endorse or promote products derived from this software without prior 
00026  *written permission. For written permission, please contact 
00027  *opentcp@opentcp.org.
00028  *
00029  *5. Products derived from this software may not be called "OpenTCP", 
00030  *nor may "OpenTCP" appear in their name, without prior written 
00031  *permission of the Viola Systems Ltd.
00032  *
00033  *THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESSED OR IMPLIED 
00034  *WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
00035  *MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
00036  *IN NO EVENT SHALL VIOLA SYSTEMS LTD. OR ITS CONTRIBUTORS BE LIABLE 
00037  *FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
00038  *CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
00039  *SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
00040  *BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
00041  *WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 
00042  *OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 
00043  *EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00044  *====================================================================
00045  *
00046  *OpenTCP is the unified open source TCP/IP stack available on a series 
00047  *of 8/16-bit microcontrollers, please see <http://www.opentcp.org>.
00048  *
00049  *For more information on how to network-enable your devices, or how to 
00050  *obtain commercial technical support for OpenTCP, please see 
00051  *<http://www.violasystems.com/>.
00052  */
00053 
00069 #include <inet/arch/mb90f553a/mb90550.h>
00070 #include <inet/datatypes.h>
00071 
00072 
00073 void init (void)
00074 {
00075 
00079         /*      Port 0  */
00080 
00081         DDR0 = 0x9F;    /* Direction. 1=O, 0=I          */
00082         PDR0 = 0x00;    /* State                                        */
00083         RDR0 = 0x00;    /* Internal Pull-Up states      */
00084         
00085         /*      Port 1  */
00086         
00087         DDR1 = 0x00;
00088         PDR1 = 0x00;
00089         RDR1 = 0xFF;
00090         
00091         /*      Port 2  */
00092         
00093         DDR2 = 0xFF;
00094         PDR2 = 0xFF;
00095         
00096         /*      Port 3  */
00097         
00098         DDR3 = 0xBF;
00099         PDR3 = 0x80;
00100         
00101         /*      Port 4  */
00102         
00103         DDR4 = 0xF3;
00104         PDR4 = 0x10;
00105         
00106         /*      Port 5  */
00107         
00108         PDR5 = 0x00;
00109         
00110         /*      Port 6  */
00111         
00112         DDR6 = 0xFF;
00113         PDR6 = 0x00;
00114         
00115         /*      Port 7  */
00116         
00117         DDR7 = 0xFF;
00118         PDR7 = 0x00;
00119         
00120         /*      Port 8  */
00121         
00122         DDR8 = 0x8E;
00123         PDR8 = 0x0C;
00124         
00125         /*      Port 9  */
00126         
00127         DDR9 = 0xFF;
00128         PDR9 = 0x00;
00129         
00130         /*      Port A  */
00131         
00132         DDRA = 0x0F;
00133         PDRA = 0x00;    
00134         
00135         
00136         /* Initialize 16 bit reload tmr 1 for slow 10 ms step SW timers */
00137         
00138         TMRLR1  =       2500;           /* 10 ms interrupt interval @ 4us step  */
00139         
00140         TMCSR1_CSL1 = 1;                /*      4 us step @ 8MHz input clock            */
00141         TMCSR1_CSL0     = 0;
00142         TMCSR1_MOD2 = 0;                /*      Disable trigger from external pin       */
00143         TMCSR1_MOD1 = 0;
00144         TMCSR1_MOD0 = 0;
00145         TMCSR1_OUTE = 0;                /*      Timer output pin disabled                       */
00146         TMCSR1_OUTL = 0;                /*      Output level (Don't care)                       */
00147         TMCSR1_RELD = 1;                /*      Enable reload operation                         */
00148         TMCSR1_INTE     = 1;            /*      Enable interrupt request                        */
00149         TMCSR1_CNTE = 1;                /*      Enable counting from trigger            */
00150         TMCSR1_TRG      = 1;            /*      Trigger it!                                                     */ 
00151 
00152         /* Initialize 16 bit reload tmr 0 for UART clock (used on speed 38400)  */
00153         
00154         TMRLR0 = 0;
00155         TMCSR0_CSL1 = 0;                /*      Divide PLL clock by 2                           */
00156         TMCSR0_CSL0     = 0;
00157         TMCSR0_MOD2 = 0;                /*      Disable trigger from external pin       */
00158         TMCSR0_MOD1 = 0;
00159         TMCSR0_MOD0 = 0;
00160         TMCSR0_OUTE = 0;                /*      Timer output pin disabled                       */
00161         TMCSR0_OUTL = 0;                /*      Output level (Don't care)                       */
00162         TMCSR0_RELD = 1;                /*      Enable reload operation                         */
00163         TMCSR0_CNTE = 0;                /*      Disable counting untill we need it      */
00164 
00165 
00166         /* Initialize the time-base timer for fast 1ms interrupt for system timer       */
00167         /* This timer is not affected by PLL and clocks always on oscillation clock     */
00168         
00169         TBTC_TBOF = 0;                  /* Clear the request                                    */
00170         TBTC_TBC1 = 0;                  /* 1.024 ms interrupt interval @ 4 MHz  */
00171         TBTC_TBC0 = 0;
00172         TBTC_TBIE = 1;                  /* Enable interrupt     request                         */
00173         
00174         
00175         /* Initialize serial port       */
00176 
00177         CDCR_MD = 1;                    /* Enable communication prescaler               */
00178         
00179         CDCR_DIV3 = 1;                  /* Set port to 9600,8,N,1                               */
00180         CDCR_DIV2 = 1;
00181         CDCR_DIV1 = 0;
00182         CDCR_DIV0 = 0;
00183         SMR_CS2 = 0;
00184         SMR_CS1 = 0;
00185         SMR_CS0 = 0;
00186         SMR_SCKE = 0;
00187         
00188         SMR_MD1 = 0;                    /* Asynchronous normal mode                             */
00189         SMR_MD0 = 0;
00190         SMR_SOE = 1;                    /* Enable TX pin                                                */
00191         SCR_RXE = 1;                    /* Enable RX                                                    */
00192         SCR_TXE = 1;                    /* Enable TX                                                    */
00193         SCR_PEN = 0;
00194         SCR_P = 0;
00195         SCR_SBL = 0;
00196         SCR_CL = 1;
00197         SCR_AD = 0;
00198         SCR_REC = 0;
00199         
00200         SSR_RIE = 0;                    /* Disable RX Interrupt request                 */
00201         SSR_TIE = 0;                    /* Disable TX Interrupt request                 */
00202         
00203         /* Kick WD      */
00204         
00205         WDTC_WTE=0;
00206 
00207 }
00208 

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