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/opentcp/arch/mb90f553a/vectors.c

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00001 /*
00002  *Copyright (c) 2000-2002 Viola Systems Ltd.
00003  *All rights reserved.
00004  *
00005  *Redistribution and use in source and binary forms, with or without 
00006  *modification, are permitted provided that the following conditions 
00007  *are met:
00008  *
00009  *1. Redistributions of source code must retain the above copyright 
00010  *notice, this list of conditions and the following disclaimer.
00011  *
00012  *2. Redistributions in binary form must reproduce the above copyright 
00013  *notice, this list of conditions and the following disclaimer in the 
00014  *documentation and/or other materials provided with the distribution.
00015  *
00016  *3. The end-user documentation included with the redistribution, if 
00017  *any, must include the following acknowledgment:
00018  *      "This product includes software developed by Viola 
00019  *      Systems (http://www.violasystems.com/)."
00020  *
00021  *Alternately, this acknowledgment may appear in the software itself, 
00022  *if and wherever such third-party acknowledgments normally appear.
00023  *
00024  *4. The names "OpenTCP" and "Viola Systems" must not be used to 
00025  *endorse or promote products derived from this software without prior 
00026  *written permission. For written permission, please contact 
00027  *opentcp@opentcp.org.
00028  *
00029  *5. Products derived from this software may not be called "OpenTCP", 
00030  *nor may "OpenTCP" appear in their name, without prior written 
00031  *permission of the Viola Systems Ltd.
00032  *
00033  *THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESSED OR IMPLIED 
00034  *WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
00035  *MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 
00036  *IN NO EVENT SHALL VIOLA SYSTEMS LTD. OR ITS CONTRIBUTORS BE LIABLE 
00037  *FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
00038  *CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
00039  *SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
00040  *BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
00041  *WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 
00042  *OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 
00043  *EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00044  *====================================================================
00045  *
00046  *OpenTCP is the unified open source TCP/IP stack available on a series 
00047  *of 8/16-bit microcontrollers, please see <http://www.opentcp.org>.
00048  *
00049  *For more information on how to network-enable your devices, or how to 
00050  *obtain commercial technical support for OpenTCP, please see 
00051  *<http://www.violasystems.com/>.
00052  */
00053 
00069 #include <inet/arch/mb90f553a/mb90550.h>
00070 #include <inet/datatypes.h>
00071 #include <inet/timers.h>
00072 #include <inet/system.h>
00073 
00074 
00075 
00076 /*------------------------------------------------------------------------
00077    InitIrqLevels()
00078 
00079    This function  pre-sets all interrupt control registers. It can be used
00080    to set all interrupt priorities in static applications. If this file
00081    contains assignments to dedicated resources, verify  that the
00082    appropriate controller is used.
00083 
00084    NOTE: value 7 disables the interrupt and value 0 sets highest priority.
00085    NOTE: Two resource interrupts always share one ICR register.
00086 */
00087 void InitIrqLevels(void)
00088 {
00089 /*  ICRxx               shared IRQs for ICR */
00090 
00091     ICR00 = 4;      /*  IRQ11
00092                         IRQ12 Time-base timer */
00093     ICR01 = 7;      /*  IRQ13     
00094                         IRQ14 */
00095     ICR02 = 7;      /*  IRQ15
00096                         IRQ16 */
00097     ICR03 = 7;      /*  IRQ17
00098                         IRQ18 */
00099     ICR04 = 7;      /*  IRQ19
00100                         IRQ20 */
00101     ICR05 = 7;      /*  IRQ21
00102                         IRQ22 */
00103     ICR06 = 7;      /*  IRQ23
00104                         IRQ24 */
00105     ICR07 = 7;      /*  IRQ25   Reload timer 0
00106                         IRQ26 */
00107     ICR08 = 5;      /*  IRQ27   Reload timer 1
00108                         IRQ28 */
00109     ICR09 = 7;      /*  IRQ29
00110                         IRQ30 */
00111     ICR10 = 7;      /*  IRQ31
00112                         IRQ32 */
00113     ICR11 = 7;      /*  IRQ33
00114                         IRQ34 */
00115     ICR12 = 7;      /*  IRQ35
00116                         IRQ36 */
00117     ICR13 = 7;      /*  IRQ37
00118                         IRQ38 */
00119     ICR14 = 3;      /*  IRQ39   UART RX
00120                         IRQ40 */
00121     ICR15 = 7;      /*  IRQ41
00122                         IRQ42 */
00123 }
00124 /*------------------------------------------------------------------------
00125    Prototypes
00126    
00127    Add your own prototypes here. Each vector definition needs is proto-
00128    type. Either do it here or include a header file containing them.
00129 
00130 */
00131 __interrupt void DefaultIRQHandler(void);
00132 __interrupt void RLDTMR1IRQHandler(void);
00133 __interrupt void SYSTMRIRQHandler(void);
00134 
00135 /*------------------------------------------------------------------------
00136    Vector definiton
00137 
00138    Use following statements to define vectors. All resource related
00139    vectors are predefined. Remaining software interrupts can be added here
00140    as well.
00141    NOTE: If software interrupts 0 to 7 are defined here, this might 
00142    conflict with the reset vector in the start-up file.
00143 */
00144 
00145 #pragma intvect DefaultIRQHandler  9    /* software interrupt 9         */
00146 #pragma intvect DefaultIRQHandler 10    /* exeception handler           */
00147 #pragma intvect DefaultIRQHandler 11    /* A/D converter                */
00148 #pragma intvect SYSTMRIRQHandler  12    /* timebase timer               */
00149 #pragma intvect DefaultIRQHandler 13    /* DTP #0                       */
00150 #pragma intvect DefaultIRQHandler 14    /* DTP #4/5                     */
00151 #pragma intvect DefaultIRQHandler 15    /* DTP #1                       */
00152 #pragma intvect DefaultIRQHandler 16    /* 8/16-bit PPG #0 (borrow)     */
00153 #pragma intvect DefaultIRQHandler 17    /* DTP #2                       */
00154 #pragma intvect DefaultIRQHandler 18    /* 8/16-bit PPG #1 (borrow)     */
00155 #pragma intvect DefaultIRQHandler 19    /* DTP #3                       */
00156 #pragma intvect DefaultIRQHandler 20    /* 8/16-bit PPG #2 (borrow)     */
00157 #pragma intvect DefaultIRQHandler 21    /* extended I/O serial #0       */
00158 #pragma intvect DefaultIRQHandler 22    /* 8/16-bit PPG #3 (borrow)     */
00159 #pragma intvect DefaultIRQHandler 23    /* extended I/O serial #1       */
00160 #pragma intvect DefaultIRQHandler 24    /* 16-bit free-run timer(overfl)*/
00161 #pragma intvect DefaultIRQHandler 25    /* 16-bit reload timer #0       */
00162 #pragma intvect DefaultIRQHandler 26    /* DTP #6/7                     */
00163 #pragma intvect RLDTMR1IRQHandler 27    /* 16-bit reload timer #1       */
00164 #pragma intvect DefaultIRQHandler 28    /* 8/16-bit PPG #4/5 (borrow)   */
00165 #pragma intvect DefaultIRQHandler 29    /* input capture CH.0           */
00166 #pragma intvect DefaultIRQHandler 30    /* input capture CH.1           */
00167 #pragma intvect DefaultIRQHandler 31    /* input capture CH.2           */
00168 #pragma intvect DefaultIRQHandler 32    /* input capture CH.3           */
00169 #pragma intvect DefaultIRQHandler 33    /* output compare CH.0          */
00170 #pragma intvect DefaultIRQHandler 34    /* output compare CH.1          */
00171 #pragma intvect DefaultIRQHandler 35    /* output compare CH.2          */
00172 #pragma intvect DefaultIRQHandler 36    /* output compare CH.3          */
00173 #pragma intvect DefaultIRQHandler 37    /* UART (transmission complete) */
00174 #pragma intvect DefaultIRQHandler 38    /* IIC #0                       */
00175 #pragma intvect DefaultIRQHandler 39    /* UART (receive complete)      */
00176 #pragma intvect DefaultIRQHandler 40    /* IIC #1                       */
00177 #pragma intvect DefaultIRQHandler 41    /* IRQ41-handler                */
00178 #pragma intvect DefaultIRQHandler 42    /* delayed interrupt            */
00179 
00180 /*------------------------------------------------------------------------
00181    DefaultIRQHandler()
00182 
00183    This function is a placeholder for all vector definitions. Either use
00184    your own placeholder or add necessary code here. 
00185 */
00186 __interrupt 
00187 void DefaultIRQHandler (void)
00188 {
00189     __DI();                              /* disable interrupts */
00190     while(1)
00191         __wait_nop();                    /* halt system */
00192 }
00193 
00194 
00195 
00196 /* 16-bit reload timer #1       */
00197 /* inline decrement timers function */
00198 #pragma inline decrement_timers
00199 
00200 __interrupt
00201 void RLDTMR1IRQHandler  (void)
00202 {
00203         /* This function is called when 16 bit reload-timer */
00204         /* overflows. Period can be changet by modifying        */
00205         /* the value of reload register TMRLR0                          */
00206         decrement_timers();
00207         TMCSR1_UF = 0;          /* Clear Interrupt request */
00208 }  
00209 
00210 
00213 __interrupt
00214 void SYSTMRIRQHandler (void)
00215 {
00216         base_timer++;
00217         
00218         TBTC_TBOF = 0;                                                  /* Clear interrupt request      */
00219 }

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