Paths for end point synch/meta_reg (SLICE_X20Y41.A4), 11 paths -------------------------------------------------------------------------------- Slack (setup path): -2.804ns (requirement - (data path - clock path skew + uncertainty)) Source: ae/ram_addr_reg_4 (FF) Destination: synch/meta_reg (FF) Requirement: 0.651ns Data Path Delay: 2.668ns (Levels of Logic = 3)(Component delays alone exceeds constraint) Clock Path Skew: -0.346ns (3.191 - 3.537) Source Clock: ac_mclk_OBUF rising at 895.182ns Destination Clock: pre_sclk rising at 895.833ns Clock Uncertainty: 0.441ns Clock Uncertainty: 0.441ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.387ns Phase Error (PE): 0.243ns Maximum Data Path at Slow Process Corner: ae/ram_addr_reg_4 to synch/meta_reg Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X19Y42.DQ Tcko 0.456 ae/ram_addr_reg<4> ae/ram_addr_reg_4 SLICE_X21Y43.B1 net (fanout=15) 0.872 ae/ram_addr_reg<4> SLICE_X21Y43.B Tilo 0.124 last_aud_addr1 last_aud_addr1 SLICE_X20Y41.B4 net (fanout=1) 0.593 last_aud_addr1 SLICE_X20Y41.B Tilo 0.124 synch/meta_reg last_aud_addr2 SLICE_X20Y41.A4 net (fanout=1) 0.452 last_aud_addr2 SLICE_X20Y41.CLK Tas 0.047 synch/meta_reg last_aud_addr3 synch/meta_reg ------------------------------------------------- --------------------------- Total 2.668ns (0.751ns logic, 1.917ns route) (28.1% logic, 71.9% route) -------------------------------------------------------------------------------- Slack (setup path): -2.788ns (requirement - (data path - clock path skew + uncertainty)) Source: ae/ram_addr_reg_0 (FF) Destination: synch/meta_reg (FF) Requirement: 0.651ns Data Path Delay: 2.652ns (Levels of Logic = 3)(Component delays alone exceeds constraint) Clock Path Skew: -0.346ns (3.191 - 3.537) Source Clock: ac_mclk_OBUF rising at 895.182ns Destination Clock: pre_sclk rising at 895.833ns Clock Uncertainty: 0.441ns Clock Uncertainty: 0.441ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.387ns Phase Error (PE): 0.243ns Maximum Data Path at Slow Process Corner: ae/ram_addr_reg_0 to synch/meta_reg Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X19Y42.BQ Tcko 0.456 ae/ram_addr_reg<4> ae/ram_addr_reg_0 SLICE_X21Y43.B2 net (fanout=16) 0.856 ae/ram_addr_reg<0> SLICE_X21Y43.B Tilo 0.124 last_aud_addr1 last_aud_addr1 SLICE_X20Y41.B4 net (fanout=1) 0.593 last_aud_addr1 SLICE_X20Y41.B Tilo 0.124 synch/meta_reg last_aud_addr2 SLICE_X20Y41.A4 net (fanout=1) 0.452 last_aud_addr2 SLICE_X20Y41.CLK Tas 0.047 synch/meta_reg last_aud_addr3 synch/meta_reg ------------------------------------------------- --------------------------- Total 2.652ns (0.751ns logic, 1.901ns route) (28.3% logic, 71.7% route) -------------------------------------------------------------------------------- Slack (setup path): -2.776ns (requirement - (data path - clock path skew + uncertainty)) Source: ae/ram_addr_reg_3 (FF) Destination: synch/meta_reg (FF) Requirement: 0.651ns Data Path Delay: 2.640ns (Levels of Logic = 3)(Component delays alone exceeds constraint) Clock Path Skew: -0.346ns (3.191 - 3.537) Source Clock: ac_mclk_OBUF rising at 895.182ns Destination Clock: pre_sclk rising at 895.833ns Clock Uncertainty: 0.441ns Clock Uncertainty: 0.441ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.387ns Phase Error (PE): 0.243ns Maximum Data Path at Slow Process Corner: ae/ram_addr_reg_3 to synch/meta_reg Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X19Y42.CMUX Tshcko 0.592 ae/ram_addr_reg<4> ae/ram_addr_reg_3 SLICE_X21Y43.B3 net (fanout=16) 0.708 ae/ram_addr_reg<3> SLICE_X21Y43.B Tilo 0.124 last_aud_addr1 last_aud_addr1 SLICE_X20Y41.B4 net (fanout=1) 0.593 last_aud_addr1 SLICE_X20Y41.B Tilo 0.124 synch/meta_reg last_aud_addr2 SLICE_X20Y41.A4 net (fanout=1) 0.452 last_aud_addr2 SLICE_X20Y41.CLK Tas 0.047 synch/meta_reg last_aud_addr3 synch/meta_reg ------------------------------------------------- --------------------------- Total 2.640ns (0.887ns logic, 1.753ns route) (33.6% logic, 66.4% route) -------------------------------------------------------------------------------- Paths for end point synch/meta_reg (SLICE_X20Y41.A1), 1 path -------------------------------------------------------------------------------- Slack (setup path): -1.989ns (requirement - (data path - clock path skew + uncertainty)) Source: ae/ram_addr_reg_11 (FF) Destination: synch/meta_reg (FF) Requirement: 0.651ns Data Path Delay: 1.854ns (Levels of Logic = 1)(Component delays alone exceeds constraint) Clock Path Skew: -0.345ns (3.191 - 3.536) Source Clock: ac_mclk_OBUF rising at 895.182ns Destination Clock: pre_sclk rising at 895.833ns Clock Uncertainty: 0.441ns Clock Uncertainty: 0.441ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.387ns Phase Error (PE): 0.243ns Maximum Data Path at Slow Process Corner: ae/ram_addr_reg_11 to synch/meta_reg Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X16Y40.CMUX Tshcko 0.650 ae/ram_addr_reg<12> ae/ram_addr_reg_11 SLICE_X20Y41.A1 net (fanout=15) 1.157 ae/ram_addr_reg<11> SLICE_X20Y41.CLK Tas 0.047 synch/meta_reg last_aud_addr3 synch/meta_reg ------------------------------------------------- --------------------------- Total 1.854ns (0.697ns logic, 1.157ns route) (37.6% logic, 62.4% route) -------------------------------------------------------------------------------- Paths for end point synch/meta_reg (SLICE_X20Y41.A2), 1 path -------------------------------------------------------------------------------- Slack (setup path): -1.828ns (requirement - (data path - clock path skew + uncertainty)) Source: ae/ram_addr_reg_12 (FF) Destination: synch/meta_reg (FF) Requirement: 0.651ns Data Path Delay: 1.693ns (Levels of Logic = 1)(Component delays alone exceeds constraint) Clock Path Skew: -0.345ns (3.191 - 3.536) Source Clock: ac_mclk_OBUF rising at 895.182ns Destination Clock: pre_sclk rising at 895.833ns Clock Uncertainty: 0.441ns Clock Uncertainty: 0.441ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.387ns Phase Error (PE): 0.243ns Maximum Data Path at Slow Process Corner: ae/ram_addr_reg_12 to synch/meta_reg Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X16Y40.DQ Tcko 0.518 ae/ram_addr_reg<12> ae/ram_addr_reg_12 SLICE_X20Y41.A2 net (fanout=15) 1.128 ae/ram_addr_reg<12> SLICE_X20Y41.CLK Tas 0.047 synch/meta_reg last_aud_addr3 synch/meta_reg ------------------------------------------------- --------------------------- Total 1.693ns (0.565ns logic, 1.128ns route) (33.4% logic, 66.6% route) -------------------------------------------------------------------------------- Hold Paths: TS_ACLK_clkout0 = PERIOD TIMEGRP "ACLK_clkout0" TS_sys_clk_pin * 0.768 HIGH 50%; --------------------------------------------------------------------------------