LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY p2s IS GENERIC ( G_PARBITS : integer := 8); PORT ( clk_i : IN std_logic; load_i : IN std_logic; shift_i : IN std_logic; par_reg_i : IN std_logic_vector(G_PARBITS -1 DOWNTO 0) := (OTHERS => '0'); ser_oq : OUT std_logic); END p2s; ARCHITECTURE FF_SHIFT OF p2s IS SIGNAL reg_q : std_logic_vector(par_reg_i'RANGE); BEGIN -- FF_SHIFT PROCESS(clk_i) begin IF rising_edge(clk_i) THEN IF load_i = '1' THEN reg_q <= par_reg_i; ELSIF shift_i = '1' THEN reg_q <= '0' & reg_q(G_PARBITS -1 DOWNTO 1); END IF; END IF; END PROCESS; ser_oq <= reg_q(0); END ARCHITECTURE FF_SHIFT; ARCHITECTURE MUXING OF p2s IS SIGNAL count_q : integer RANGE G_PARBITS - 1 DOWNTO 0; SIGNAL overflow : boolean; SIGNAL ser : std_logic; BEGIN -- MUXING overflow <= count_q = G_PARBITS - 1; --counter as mux selector PROCESS(clk_i) BEGIN IF rising_edge(clk_i) THEN --all outputs shall be buffered ser_oq <= ser; IF load_i = '1' OR overflow THEN count_q <= 0; ELSIF shift_i = '1' THEN count_q <= count_q + 1; END IF; END IF; END PROCESS; --the muxer ser <= par_reg_i(count_q); END ARCHITECTURE MUXING; LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY test_env IS GENERIC ( G_PARBITS : integer := 8); PORT ( clk_pin_i : IN std_logic; load_pin_i : IN std_logic; shift_pin_i : IN std_logic; par_reg_pin_i : IN std_logic_vector(G_PARBITS -1 DOWNTO 0) := (OTHERS => '0'); ser_shift_pin_oq : OUT std_logic; ser_mux_pin_oq : OUT std_logic); END test_env; ARCHITECTURE behave OF test_env IS --using IOB-FF SIGNAL load_int_q : std_logic; SIGNAL shift_int_q : std_logic; SIGNAL par_reg_int_q : std_logic_vector(G_PARBITS -1 DOWNTO 0); SIGNAL ser_shift_int : std_logic; SIGNAL ser_mux_int : std_logic; BEGIN -- behave PROCESS(clk_pin_i) BEGIN IF rising_edge(clk_pin_i) THEN load_int_q <= load_pin_i; shift_int_q <= shift_pin_i; par_reg_int_q <= par_reg_pin_i; ser_shift_pin_oq <= ser_shift_int; ser_mux_pin_oq <= ser_mux_int; END IF; END PROCESS; mux_gh: ENTITY work.p2s(MUXING) GENERIC MAP ( G_PARBITS => G_PARBITS) PORT MAP ( clk_i => clk_pin_i, load_i => load_int_q, shift_i => shift_int_q, par_reg_i => par_reg_int_q, ser_oq => ser_mux_int); shift_gh: ENTITY work.p2s(FF_SHIFT) GENERIC MAP ( G_PARBITS => G_PARBITS) PORT MAP ( clk_i => clk_pin_i, load_i => load_int_q, shift_i => shift_int_q, par_reg_i => par_reg_int_q, ser_oq => ser_shift_int); END behave;