module adr_demux( clk, // Clock Eingang adress, // Eingangsadresse sel, // Unterscheidundg zwischen Slave A und Slave B slave_a1, // Select slave A slave_b1); // Select slave B // Info Codes input clk, sel; input [4:0] adress; output [31:0] slave_a1; output [31:0] slave_b1; //reg [4:0] adress_reg; reg sel_A_B; reg [31:0] slave_a1; reg [31:0] slave_b1; always@(posedge clk) begin: select_output //adress_reg = adress; sel_A_B = sel; case(adress) 5'b00000: begin if(!sel_A_B) slave_a1 <= 32'b00000000000000000000000000000001; else slave_b1 <= 32'b00000000000000000000000000000001; end 5'b00001: begin if(!sel_A_B) slave_a1 <= 32'b00000000000000000000000000000010; else slave_b1 <= 32'b00000000000000000000000000000010; end 5'b00010: begin if(!sel_A_B) slave_a1 <= 32'd4; else slave_b1 <= 32'b00000000000000000000000000000100; end 5'b00011: begin if(!sel_A_B) slave_a1 <= 32'b00000000000000000000000000001000; else slave_b1 <= 32'b00000000000000000000000000001000; end 5'b00100: begin if(!sel_A_B) slave_a1 <= 32'b00000000000000000000000000010000; else slave_b1 <= 32'b00000000000000000000000000010000; end 5'b00101: begin if(!sel_A_B) slave_a1 <= 32'b00000000000000000000000000100000; else slave_b1 <= 32'b00000000000000000000000000100000; end 5'b00110: begin if(!sel_A_B) slave_a1 <= 32'b00000000000000000000000001000000; else slave_b1 <= 32'b00000000000000000000000001000000; end 5'b00111: begin if(!sel_A_B) slave_a1 <= 32'b00000000000000000000000010000000; else slave_b1 <= 32'b00000000000000000000000010000000; end 5'b01000: begin if(!sel_A_B) slave_a1 <= 32'b00000000000000000000000100000000; else slave_b1 <= 32'b00000000000000000000000100000000; end 5'b01001: begin if(!sel_A_B) slave_a1 <= 32'b00000000000000000000001000000000; else slave_b1 <= 32'b00000000000000000000001000000000; end 5'b01010: begin if(!sel_A_B) slave_a1 <= 32'b00000000000000000000010000000000; else slave_b1 <= 32'b00000000000000000000010000000000; end 5'b01011: begin if(!sel_A_B) slave_a1 <= 32'b00000000000000000000100000000000; else slave_b1 <= 32'b00000000000000000000100000000000; end 5'b01100: begin if(!sel_A_B) slave_a1 <= 32'b00000000000000000001000000000000; else slave_b1 <= 32'b00000000000000000001000000000000; end 5'b01101: begin if(!sel_A_B) slave_a1 <= 32'b00000000000000000010000000000000; else slave_b1 <= 32'b00000000000000000010000000000000; end 5'b01110: begin if(!sel_A_B) slave_a1 <= 32'b00000000000000000100000000000000; else slave_b1 <= 32'b00000000000000000100000000000000; end 5'b01111: begin if(!sel_A_B) slave_a1 <= 32'b00000000000000001000000000000000; else slave_b1 <= 32'b00000000000000001000000000000000; end 5'b10000: begin if(!sel_A_B) slave_a1 <= 32'b00000000000000010000000000000000; else slave_b1 <= 32'b00000000000000010000000000000000; end 5'b10001: begin if(!sel_A_B) slave_a1 <= 32'b00000000000000100000000000000000; else slave_b1 <= 32'b00000000000000100000000000000000; end 5'b10010: begin if(!sel_A_B) slave_a1 <= 32'b00000000000001000000000000000000; else slave_b1 <= 32'b00000000000001000000000000000000; end 5'b10011: begin if(!sel_A_B) slave_a1 <= 32'b00000000000010000000000000000000; else slave_b1 <= 32'b00000000000010000000000000000000; end 5'b10100: begin if(!sel_A_B) slave_a1 <= 32'b00000000000100000000000000000000; else slave_b1 <= 32'b00000000000100000000000000000000; end 5'b10101: begin if(!sel_A_B) slave_a1 <= 32'b00000000001000000000000000000000; else slave_b1 <= 32'b00000000001000000000000000000000; end 5'b10110: begin if(!sel_A_B) slave_a1 <= 32'b00000000010000000000000000000000; else slave_b1 <= 32'b00000000010000000000000000000000; end 5'b10111: begin if(!sel_A_B) slave_a1 <= 32'b00000000100000000000000000000000; else slave_b1 <= 32'b00000000100000000000000000000000; end 5'b11000: begin if(!sel_A_B) slave_a1 <= 32'b00000001000000000000000000000000; else slave_b1 <= 32'b00000001000000000000000000000000; end 5'b11001: begin if(!sel_A_B) slave_a1 <= 32'b00000010000000000000000000000000; else slave_b1 <= 32'b00000010000000000000000000000000; end 5'b11010: begin if(!sel_A_B) slave_a1 <= 32'b00000100000000000000000000000000; else slave_b1 <= 32'b00000100000000000000000000000000; end 5'b11011: begin if(!sel_A_B) slave_a1 <= 32'b00001000000000000000000000000000; else slave_b1 <= 32'b00001000000000000000000000000000; end 5'b11100: begin if(!sel_A_B) slave_a1 <= 32'b00010000000000000000000000000000; else slave_b1 <= 32'b00010000000000000000000000000000; end 5'b11101: begin if(!sel_A_B) slave_a1 <= 32'b00100000000000000000000000000000; else slave_b1 <= 32'b00100000000000000000000000000000; end 5'b11110: begin if(!sel_A_B) slave_a1 <= 32'b01000000000000000000000000000000; else slave_b1 <= 32'b01000000000000000000000000000000; end 5'b11111: begin if(!sel_A_B) slave_a1 <= 32'b10000000000000000000000000000000; else slave_b1 <= 32'b10000000000000000000000000000000; end endcase end //assign slave_a1 = slave_a; //assign slave_b1 = slave_b; endmodule