/* SAM3XA PMC Header (c) S. Raase, 2015 */ #ifndef _DEVICES_PMC_H_ #define _DEVICES_PMC_H_ typedef struct { reg32_wo PMC_SCER; /* System Clock Enable Register */ reg32_wo PMC_SCDR; /* System Clock Disable Register */ reg32_ro PMC_SCSR; /* System Clock Status Register */ reg32_und Reserved1; /* Reserved */ reg32_wo PMC_PCER0; /* Peripheral Clock Enable Register 0 */ reg32_wo PMC_PCDR0; /* Peripheral Clock Disable Register 0 */ reg32_ro PMC_PCSR0; /* Peripheral Clock Status Register 0 */ reg32_rw CKGR_UCKR; /* UTMI Clock Register */ reg32_rw CKGR_MOR; /* Main Oscillator Register */ reg32_ro CKGR_MCFR; /* Main Clock Frequency Register */ reg32_rw CKGR_PLLAR; /* PLLA Register */ reg32_und Reserved2; /* Reserved */ reg32_rw PMC_MCKR; /* Master Clock Register */ reg32_und Reserved3; /* Reserved */ reg32_rw PMC_USB; /* USB Clock Register */ reg32_und Reserved4; /* Reserved */ reg32_rw PMC_PCK0; /* Programmable Clock 0 Register */ reg32_rw PMC_PCK1; /* Programmable Clock 1 Register */ reg32_rw PMC_PCK2; /* Programmable Clock 2 Register */ reg32_und Reserved5[5]; /* Reserved */ reg32_wo PMC_IER; /* Interrupt Enable Register */ reg32_wo PMC_IDR; /* Interrupt Disable Register */ reg32_ro PMC_SR; /* Status Register */ reg32_ro PMC_IMR; /* Interrupt Mask Register */ reg32_rw PMC_FSMR; /* Fast Startup Mode Register */ reg32_rw PMC_FSPR; /* Fast Startup Polarity Register */ reg32_wo PMC_FOCR; /* Fault Output Clear Register */ reg32_und Reserved6[26]; /* Reserved */ reg32_rw PMC_WPMR; /* Write Protect Mode Register */ reg32_ro PMC_WPSR; /* Write Protect Status Register */ reg32_und Reserved[5]; /* Reserved */ reg32_wo PMC_PCER1; /* Peripheral Clock Enable Register 1 */ reg32_wo PMC_PCDR1; /* Peripheral Clock Disable Register 1 */ reg32_ro PMC_PCSR1; /* Peripheral Clock Status Register 1 */ reg32_rw PMC_PCR; /* Peripheral Control Register */ } regs_pmc; /* System Clock (Enable/Disable/Status) Register */ #define PMC_SCER_UOTGCLK (1 << 5) #define PMC_SCER_PCK0 (1 << 8) #define PMC_SCER_PCK1 (1 << 9) #define PMC_SCER_PCK2 (1 << 10) /* PMC Peripheral Clock (Enable/Disable/Status) Register 0 */ #define PMC_PCER0_PID2 (1 << 2) #define PMC_PCER0_PID3 (1 << 3) #define PMC_PCER0_PID4 (1 << 4) #define PMC_PCER0_PID5 (1 << 5) #define PMC_PCER0_PID6 (1 << 6) #define PMC_PCER0_PID7 (1 << 7) #define PMC_PCER0_PID8 (1 << 8) #define PMC_PCER0_PID9 (1 << 9) #define PMC_PCER0_PID10 (1 << 10) #define PMC_PCER0_PID11 (1 << 11) #define PMC_PCER0_PID12 (1 << 12) #define PMC_PCER0_PID13 (1 << 13) #define PMC_PCER0_PID14 (1 << 14) #define PMC_PCER0_PID15 (1 << 15) #define PMC_PCER0_PID16 (1 << 16) #define PMC_PCER0_PID17 (1 << 17) #define PMC_PCER0_PID18 (1 << 18) #define PMC_PCER0_PID19 (1 << 19) #define PMC_PCER0_PID20 (1 << 20) #define PMC_PCER0_PID21 (1 << 21) #define PMC_PCER0_PID22 (1 << 22) #define PMC_PCER0_PID23 (1 << 23) #define PMC_PCER0_PID24 (1 << 24) #define PMC_PCER0_PID25 (1 << 25) #define PMC_PCER0_PID26 (1 << 26) #define PMC_PCER0_PID27 (1 << 27) #define PMC_PCER0_PID28 (1 << 28) #define PMC_PCER0_PID29 (1 << 29) #define PMC_PCER0_PID30 (1 << 30) #define PMC_PCER0_PID31 (1 << 31) /* PMC UTMI Clock Configuration Register */ #define CKGR_UCKR_UPLLEN (1 << 16) #define CKGR_UCKR_UPLLCOUNT(val) (((val) << 20) & (0xF << 20) /* PMC Clock Generator Main Oscillator Register */ #define CKGR_MOR_MOSCXTEN (1 << 0) #define CKGR_MOR_MOSCXTBY (1 << 1) #define CKGR_MOR_MOSCRCEN (1 << 3) #define CKGR_MOR_MOSCRCF(val) (((val) << 4) & (0x7 << 4)) #define CKGR_MOR_MOSCXTST(val) (((val) << 8) & (0xFF << 8)) #define CKGR_MOR_KEY(val) (((val) << 16) & (0xFF << 16)) #define CKGR_MOR_MOSCSEL (1 << 24) #define CKGR_MOR_CFDEN (1 << 25) /* PMC Clock Generator Main Clock Frequency Register */ #define CKGR_MCFR_MAINF(val) (((val) << 0) & (0xFFFF << 0)) #define CKGR_MCFR_MAINFRDY (1 << 16) /* PMC Clock Generator PLLA Register */ #define CKGR_PLLAR_DIVA(val) (((val) << 0) & (0xFF << 0)) #define CKGR_PLLAR_PLLACOUNT(val) (((val) << 8) & (0x3F << 8)) #define CKGR_PLLAR_MULA(val) (((val) << 16) & (0x7FF << 16)) #define CKGR_PLLAR_ONE (1 << 29) /* PMC Master Clock Register */ #define PMC_MCKR_CSS(val) (((val) << 0) & (0x3 << 0)) #define PMC_MCKR_PRES(val) (((val) << 4) & (0x7 << 4)) #define PMC_MCKR_PLLADIV2 (1 << 12) #define PMC_MCKR_UPLLDIV2 (1 << 13) /* PMC USB Clock Register */ #define PMC_USB_USBS (1 << 0) #define PMC_USB_USBDIV(val) (((val) << 8) & (0xF << 8)) /* PMC Programmable Clock Register */ #define PMC_PCKx_CSS(val) (((val) << 0) & (0x7 << 0)) #define PMC_PCKx_PRES(val) (((val) << 4) & (0x7 << 4)) /* PMC Interrupt (Enable/Disable/Mask) Register */ #define PMC_IER_MOSCXTS (1 << 0) #define PMC_IER_LOCKA (1 << 1) #define PMC_IER_MCKRDY (1 << 3) #define PMC_IER_LOCKU (1 << 6) #define PMC_IER_PCKRDY0 (1 << 8) #define PMC_IER_PCKRDY1 (1 << 9) #define PMC_IER_PCKRDY2 (1 << 10) #define PMC_IER_MOSCSELS (1 << 16) #define PMC_IER_MOSCRCS (1 << 17) #define PMC_IER_CFDEV (1 << 18) /* PMC Status Register */ #define PMC_SR_MOSCXTS (1 << 0) #define PMC_SR_LOCKA (1 << 1) #define PMC_SR_MCKRDY (1 << 3) #define PMC_SR_LOCKU (1 << 6) #define PMC_SR_OSCSELS (1 << 7) #define PMC_SR_PCKRDY0 (1 << 8) #define PMC_SR_PCKRDY1 (1 << 9) #define PMC_SR_PCKRDY2 (1 << 10) #define PMC_SR_MOSCSELS (1 << 16) #define PMC_SR_MOSCRCS (1 << 17) #define PMC_SR_CFDEV (1 << 18) #define PMC_SR_CFDS (1 << 19) #define PMC_SR_FOS (1 << 20) /* PMC Fast Startup Mode Register */ #define PMC_FSMR_FSTT0 (1 << 0) #define PMC_FSMR_FSTT1 (1 << 1) #define PMC_FSMR_FSTT2 (1 << 2) #define PMC_FSMR_FSTT3 (1 << 3) #define PMC_FSMR_FSTT4 (1 << 4) #define PMC_FSMR_FSTT5 (1 << 5) #define PMC_FSMR_FSTT6 (1 << 6) #define PMC_FSMR_FSTT7 (1 << 7) #define PMC_FSMR_FSTT8 (1 << 8) #define PMC_FSMR_FSTT9 (1 << 9) #define PMC_FSMR_FSTT10 (1 << 10) #define PMC_FSMR_FSTT11 (1 << 11) #define PMC_FSMR_FSTT12 (1 << 12) #define PMC_FSMR_FSTT13 (1 << 13) #define PMC_FSMR_FSTT14 (1 << 14) #define PMC_FSMR_FSTT15 (1 << 15) #define PMC_FSMR_RTTAL (1 << 16) #define PMC_FSMR_RTCAL (1 << 17) #define PMC_FSMR_USBAL (1 << 18) #define PMC_FSMR_LPM (1 << 20) /* PMC Fast Startup Polarity Register */ #define PMC_FSPR_FSTP0 (1 << 0) #define PMC_FSPR_FSTP1 (1 << 1) #define PMC_FSPR_FSTP2 (1 << 2) #define PMC_FSPR_FSTP3 (1 << 3) #define PMC_FSPR_FSTP4 (1 << 4) #define PMC_FSPR_FSTP5 (1 << 5) #define PMC_FSPR_FSTP6 (1 << 6) #define PMC_FSPR_FSTP7 (1 << 7) #define PMC_FSPR_FSTP8 (1 << 8) #define PMC_FSPR_FSTP9 (1 << 9) #define PMC_FSPR_FSTP10 (1 << 10) #define PMC_FSPR_FSTP11 (1 << 11) #define PMC_FSPR_FSTP12 (1 << 12) #define PMC_FSPR_FSTP13 (1 << 13) #define PMC_FSPR_FSTP14 (1 << 14) #define PMC_FSPR_FSTP15 (1 << 15) /* PMC Fault Output Clear Register */ #define PMC_FOCR_FOCLR (1 << 0) /* PMC Write Protect Mode Register */ #define PMC_WPMR_WPEN (1 << 0) #define PMC_WPMR_WPKEY(val) (((val) << 8) & 0xFFFFFF << 8) /* PMC Write Protect Status Register */ #define PMC_WPSR_WPVS (1 << 0) #define PMC_WPSR_WPVSRC(val) (((val) << 8) & 0xFFFF << 8) /* PMC Peripheral Clock (Enable/Disable/Status) Register 1 */ #define PMC_PCER1_PID32 (1 << 0) #define PMC_PCER1_PID33 (1 << 1) #define PMC_PCER1_PID34 (1 << 2) #define PMC_PCER1_PID35 (1 << 3) #define PMC_PCER1_PID36 (1 << 4) #define PMC_PCER1_PID37 (1 << 5) #define PMC_PCER1_PID38 (1 << 6) #define PMC_PCER1_PID39 (1 << 7) #define PMC_PCER1_PID40 (1 << 8) #define PMC_PCER1_PID41 (1 << 9) #define PMC_PCER1_PID42 (1 << 10) #define PMC_PCER1_PID43 (1 << 11) #define PMC_PCER1_PID44 (1 << 12) /* PMC Peripheral Control Register */ #define PMC_PCR_PID(val) (((val) << 0) & (0x3F << 0)) #define PMC_PCR_CMD (1 << 12) #define PMC_PCR_DIV(val) (((val) << 16) & (0x3 << 16)) #endif /* _DEVICES_PMC_H_ */