/* SAM3XA SUPC Header (c) S. Raase, 2015 */ #ifndef _DEVICES_SUPC_H_ #define _DEVICES_SUPC_H_ typedef struct { reg32_wo SUPC_CR; /* Control Register */ reg32_rw SUPC_SMMR; /* Supply Monitor Mode Register */ reg32_rw SUPC_MR; /* Mode Register */ reg32_rw SUPC_WUMR; /* Wake Up Mode Register */ reg32_rw SUPC_WUIR; /* Wake Up Inputs Register */ reg32_ro SUPC_SR; /* Status Register */ } regs_supc; /* Control Register */ #define SUPC_CR_VROFF (1 << 2) #define SUPC_CR_XTALSEL (1 << 3) #define SUPC_CR_KEY(val) (((val) << 24) & (0xFF) << 24) /* Supply Monitor Mode Register */ #define SUPC_SMMR_SMTH(val) (((val) << 0) & (0xF << 0)) #define SUPC_SMMR_SMSMPL(val) (((val) << 8) & (0x7 << 8)) #define SUPC_SMMR_SMRSTEN (1 << 12) #define SUPC_SMMR_SMIEN (1 << 13) /* Mode Register */ #define SUPC_MR_BODRSTEN (1 << 12) #define SUPC_MR_BODDIS (1 << 13) #define SUPC_MR_VDDIORDY_ONREG (1 << 14) #define SUPC_MR_OSCBYPASS (1 << 20) #define SUPC_MR_KEY(val) (((val) << 24) & (0xFF << 24)) /* Wake Up Mode Register */ #define SUPC_WUMR_FWUPEN (1 << 0) #define SUPC_WUMR_SMEN (1 << 1) #define SUPC_WUMR_RTTEN (1 << 2) #define SUPC_WUMR_RTCEN (1 << 3) #define SUPC_WUMR_FWUPDBC(val) (((val) << 8) & (0x7 << 8)) #define SUPC_WUMR_WKUPDBC(val) (((val) << 12) & (0x7 << 12)) /* Wake Up Inputs Register */ #define SUPC_WUIR_WKUPEN0 (1 << 0) #define SUPC_WUIR_WKUPEN1 (1 << 1) #define SUPC_WUIR_WKUPEN2 (1 << 2) #define SUPC_WUIR_WKUPEN3 (1 << 3) #define SUPC_WUIR_WKUPEN4 (1 << 4) #define SUPC_WUIR_WKUPEN5 (1 << 5) #define SUPC_WUIR_WKUPEN6 (1 << 6) #define SUPC_WUIR_WKUPEN7 (1 << 7) #define SUPC_WUIR_WKUPEN8 (1 << 8) #define SUPC_WUIR_WKUPEN9 (1 << 9) #define SUPC_WUIR_WKUPEN10 (1 << 10) #define SUPC_WUIR_WKUPEN11 (1 << 11) #define SUPC_WUIR_WKUPEN12 (1 << 12) #define SUPC_WUIR_WKUPEN13 (1 << 13) #define SUPC_WUIR_WKUPEN14 (1 << 14) #define SUPC_WUIR_WKUPEN15 (1 << 15) #define SUPC_WUIR_WKUPT0 (1 << 0) #define SUPC_WUIR_WKUPT1 (1 << 1) #define SUPC_WUIR_WKUPT2 (1 << 2) #define SUPC_WUIR_WKUPT3 (1 << 3) #define SUPC_WUIR_WKUPT4 (1 << 4) #define SUPC_WUIR_WKUPT5 (1 << 5) #define SUPC_WUIR_WKUPT6 (1 << 6) #define SUPC_WUIR_WKUPT7 (1 << 7) #define SUPC_WUIR_WKUPT8 (1 << 8) #define SUPC_WUIR_WKUPT9 (1 << 9) #define SUPC_WUIR_WKUPT10 (1 << 10) #define SUPC_WUIR_WKUPT11 (1 << 11) #define SUPC_WUIR_WKUPT12 (1 << 12) #define SUPC_WUIR_WKUPT13 (1 << 13) #define SUPC_WUIR_WKUPT14 (1 << 14) #define SUPC_WUIR_WKUPT15 (1 << 15) /* Status Register */ #define SUPC_SR_FWUPS (1 << 0) #define SUPC_SR_WKUPS (1 << 1) #define SUPC_SR_SMWS (1 << 2) #define SUPC_SR_BODRSTS (1 << 3) #define SUPC_SR_SMRSTS (1 << 4) #define SUPC_SR_SMS (1 << 5) #define SUPC_SR_SMOS (1 << 6) #define SUPC_SR_OSCSEL (1 << 7) #define SUPC_SR_FWUPIS (1 << 12) #define SUPC_SR_WKUPIS0 (1 << 16) #define SUPC_SR_WKUPIS1 (1 << 17) #define SUPC_SR_WKUPIS2 (1 << 18) #define SUPC_SR_WKUPIS3 (1 << 19) #define SUPC_SR_WKUPIS4 (1 << 20) #define SUPC_SR_WKUPIS5 (1 << 21) #define SUPC_SR_WKUPIS6 (1 << 22) #define SUPC_SR_WKUPIS7 (1 << 23) #define SUPC_SR_WKUPIS8 (1 << 24) #define SUPC_SR_WKUPIS9 (1 << 25) #define SUPC_SR_WKUPIS10 (1 << 26) #define SUPC_SR_WKUPIS11 (1 << 27) #define SUPC_SR_WKUPIS12 (1 << 28) #define SUPC_SR_WKUPIS13 (1 << 29) #define SUPC_SR_WKUPIS14 (1 << 30) #define SUPC_SR_WKUPIS15 (1 << 31) #endif /* _DEVICES_SUPC_H_ */