module dec( clk1, // Clock Eingang clk2, data_out, data1_in); parameter FRAMESIZE = 14; input clk1, clk2; input data_in; output [FRAMESIZE:0] data_out; reg [FRAMESIZE-1:0] data_in; reg [FRAMESIZE-1:0] data_out; reg [(FRAMESIZE/2)-1:0] dec_data; integer i=0; integer j; integer k=0; always @(posedge clk1) begin: store_data if (i