Reading design: KUSB_IO_FLEX.prj ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/READEREncoderDetect.vhd" in Library work. Architecture readerencoderdetect_arch of Entity readerencoderdetect is up to date. Compiling vhdl file "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/READERMemoryAddrDataWrite.vhd" in Library work. Architecture readermemoryaddrdatawrite_arch of Entity readermemoryaddrdatawrite is up to date. Compiling vhdl file "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/READERMemoryWriteStatemachine.vhd" in Library work. Architecture readermemorywritestatemachine_arch of Entity readermemorywritestatemachine is up to date. Compiling vhdl file "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/READERMemoryReadThroughRAM.vhd" in Library work. Architecture readthroughram_arch of Entity readthroughram is up to date. Compiling vhdl file "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/READERCONTROLSync.vhd" in Library work. Architecture readercontrolsync_arch of Entity readercontrolsync is up to date. Compiling vhdl file "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/READERCONTROLReaderStateMachine.vhd" in Library work. Architecture readercontrolreaderstatemachine_arch of Entity readercontrolreaderstatemachine is up to date. Compiling vhdl file "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/READERCONTROLSpurStateMachine.vhd" in Library work. Architecture readercontrolspurstatemachine_arch of Entity readercontrolspurstatemachine is up to date. Compiling vhdl file "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/READERRegister.vhd" in Library work. Architecture readerregister_arch of Entity readerregister is up to date. Compiling vhdl file "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/READERInOutMapper.vhd" in Library work. Architecture readerinoutmapper_arch of Entity readerinoutmapper is up to date. Compiling vhdl file "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/READERCONTROL.vhd" in Library work. Architecture readercontrol_arch of Entity readercontrol is up to date. Compiling vhdl file "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/READERMemory.vhd" in Library work. Architecture readermemory_arch of Entity readermemory is up to date. Compiling vhdl file "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/READEREdgeDetect.vhd" in Library work. Architecture readeredgedetect_arch of Entity readeredgedetect is up to date. Compiling vhdl file "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/READERStepCount.vhd" in Library work. Architecture readerstepcount_arch of Entity readerstepcount is up to date. Compiling vhdl file "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/READERWindowDetect.vhd" in Library work. Architecture readerwindowdetect_arch of Entity readerwindowdetect is up to date. Compiling vhdl file "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/CAPTURERegister.vhd" in Library work. Architecture captureregister_arch of Entity captureregister is up to date. Compiling vhdl file "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/CAPTUREInOutMapper.vhd" in Library work. Architecture captureinoutmapper_arch of Entity captureinoutmapper is up to date. Compiling vhdl file "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/CAPTURELogic.vhd" in Library work. Architecture capturelogic_arch of Entity capturelogic is up to date. Compiling vhdl file "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/STEPMATCHRegister.vhd" in Library work. Architecture stepmatchregister_arch of Entity stepmatchregister is up to date. Compiling vhdl file "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/STEPMATCHLogic.vhd" in Library work. Architecture stepmatchlogic_arch of Entity stepmatchlogic is up to date. Compiling vhdl file "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/COUNTERRegister.vhd" in Library work. Architecture counterregister_arch of Entity counterregister is up to date. Compiling vhdl file "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/COUNTERInOutMapper.vhd" in Library work. Architecture counterinoutmapper_arch of Entity counterinoutmapper is up to date. Compiling vhdl file "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/COUNTEREncoderDetect.vhd" in Library work. Architecture counterencoderdetect_arch of Entity counterencoderdetect is up to date. Compiling vhdl file "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/COUNTERStepCount.vhd" in Library work. Architecture counterstepcount_arch of Entity counterstepcount is up to date. Compiling vhdl file "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/COUNTERSoftEncoder.vhd" in Library work. Architecture countersoftencoder_arch of Entity countersoftencoder is up to date. Compiling vhdl file "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/DIGITALIORegister.vhd" in Library work. Architecture digitalioregister_arch of Entity digitalioregister is up to date. Compiling vhdl file "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/DIGITALIOInputFilter.vhd" in Library work. Architecture digitalioinputfilter_arch of Entity digitalioinputfilter is up to date. Compiling vhdl file "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/DIGITALIOEdgeDetect.vhd" in Library work. Architecture digitalioedgedetect_arch of Entity digitalioedgedetect is up to date. Compiling vhdl file "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/DIGITALIOSharedOutputs.vhd" in Library work. Architecture digitaliosharedoutputs_arch of Entity digitaliosharedoutputs is up to date. Compiling vhdl file "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/uCINTERFACESync.vhd" in Library work. Architecture ucinterfacesync_arch of Entity ucinterfacesync is up to date. Compiling vhdl file "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/uCINTERFACEAccessDetection.vhd" in Library work. Architecture ucinterfaceaccessdetection_arch of Entity ucinterfaceaccessdetection is up to date. Compiling vhdl file "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/uCINTERFACERegister.vhd" in Library work. Entity compiled. Entity (Architecture ) compiled. Compiling vhdl file "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/uCINTERFACE.vhd" in Library work. Architecture ucinterface_arch of Entity ucinterface is up to date. Compiling vhdl file "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/CLOCKManager.vhd" in Library work. Architecture clockmanager_arch of Entity clockmanager is up to date. Compiling vhdl file "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/DIGITALIO.vhd" in Library work. Architecture digitalio_arch of Entity digitalio is up to date. Compiling vhdl file "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/COUNTER.vhd" in Library work. Architecture counter_arch of Entity counter is up to date. Compiling vhdl file "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/STEPMATCH.vhd" in Library work. Architecture stepmatch_arch of Entity stepmatch is up to date. Compiling vhdl file "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/CAPTURE.vhd" in Library work. Architecture capture_arch of Entity capture is up to date. Compiling vhdl file "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/READER.vhd" in Library work. Architecture reader_arch of Entity reader is up to date. Compiling vhdl file "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/KUSB_IO_FLEX.vhd" in Library work. Architecture kusb_io_flex_arch of Entity kusb_io_flex is up to date. ========================================================================= * Design Hierarchy Analysis * ========================================================================= Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). WARNING:Xst:819 - "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/READERRegister.vhd" line 270: The following signals are missing in the process sensitivity list: STEP_COUNT. Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Performing bidirectional port resolution... INFO:Xst:2561 - Always blocking tristate driving signal in unit is removed. INFO:Xst:2561 - Always blocking tristate driving signal in unit is removed. INFO:Xst:2561 - Always blocking tristate driving signal in unit is removed. INFO:Xst:2561 - Always blocking tristate driving signal in unit is removed. INFO:Xst:2561 - Always blocking tristate driving signal in unit is removed. INFO:Xst:2561 - Always blocking tristate driving signal in unit is removed. INFO:Xst:2561 - Always blocking tristate driving signal in unit is removed. INFO:Xst:2561 - Always blocking tristate driving signal in unit is removed. INFO:Xst:2561 - Always blocking tristate driving signal in unit is removed. INFO:Xst:2561 - Always blocking tristate driving signal in unit is removed. INFO:Xst:2561 - Always blocking tristate driving signal in unit is removed. INFO:Xst:2561 - Always blocking tristate driving signal in unit is removed. INFO:Xst:2561 - Always blocking tristate driving signal in unit is removed. INFO:Xst:2561 - Always blocking tristate driving signal in unit is removed. INFO:Xst:2561 - Always blocking tristate driving signal in unit is removed. INFO:Xst:2561 - Always blocking tristate driving signal in unit is removed. Synthesizing Unit . Related source file is "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/CLOCKManager.vhd". Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/uCINTERFACESync.vhd". Found 1-bit register for signal . Found 8-bit register for signal . Found 1-bit register for signal . Found 32-bit tristate buffer for signal . Found 1-bit register for signal . Found 8-bit tristate buffer for signal . Found 1-bit register for signal . Found 16-bit register for signal . Found 32-bit register for signal . Found 32-bit register for signal . Summary: inferred 92 D-type flip-flop(s). inferred 64 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/uCINTERFACEAccessDetection.vhd". WARNING:Xst:647 - Input > is never used. Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 2 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/uCINTERFACERegister.vhd". Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 8-bit register for signal . Summary: inferred 8 D-type flip-flop(s). inferred 32 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/DIGITALIORegister.vhd". WARNING:Xst:2563 - Inout > is never assigned. Tied to value Z. WARNING:Xst:2563 - Inout > is never assigned. Tied to value Z. WARNING:Xst:2563 - Inout > is never assigned. Tied to value Z. WARNING:Xst:2563 - Inout > is never assigned. Tied to value Z. WARNING:Xst:2563 - Inout > is never assigned. Tied to value Z. WARNING:Xst:2563 - Inout > is never assigned. Tied to value Z. WARNING:Xst:2563 - Inout > is never assigned. Tied to value Z. WARNING:Xst:2563 - Inout > is never assigned. Tied to value Z. WARNING:Xst:2563 - Inout > is never assigned. Tied to value Z. WARNING:Xst:2563 - Inout > is never assigned. Tied to value Z. WARNING:Xst:2563 - Inout > is never assigned. Tied to value Z. WARNING:Xst:2563 - Inout > is never assigned. Tied to value Z. WARNING:Xst:2563 - Inout > is never assigned. Tied to value Z. WARNING:Xst:2563 - Inout > is never assigned. Tied to value Z. WARNING:Xst:2563 - Inout > is never assigned. Tied to value Z. WARNING:Xst:2563 - Inout > is never assigned. Tied to value Z. Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 1-bit tristate buffer for signal >. Found 3-bit register for signal . Found 1-bit register for signal . Found 12-bit register for signal . Found 12-bit register for signal . Summary: inferred 30 D-type flip-flop(s). inferred 32 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/DIGITALIOInputFilter.vhd". Found 12-bit register for signal . Found 12-bit register for signal . Found 12-bit register for signal . Found 12-bit register for signal . Found 12-bit register for signal . Found 12-bit register for signal . Found 12-bit register for signal . Summary: inferred 84 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/DIGITALIOEdgeDetect.vhd". Found 12-bit register for signal . Found 12-bit register for signal . Summary: inferred 24 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/DIGITALIOSharedOutputs.vhd". Found 12-bit tristate buffer for signal . Found 1-bit register for signal > created at line 74. Found 1-bit register for signal > created at line 74. Found 1-bit register for signal > created at line 74. Found 1-bit register for signal > created at line 74. Found 1-bit register for signal > created at line 74. Found 1-bit xor2 for signal $xor0000> created at line 82. Found 1-bit register for signal > created at line 74. Found 1-bit register for signal > created at line 74. Found 1-bit register for signal > created at line 74. Found 1-bit register for signal > created at line 74. Found 1-bit xor2 for signal $xor0000> created at line 83. Found 1-bit register for signal > created at line 74. Found 1-bit register for signal > created at line 74. Found 1-bit register for signal > created at line 74. Found 1-bit register for signal > created at line 74. Found 1-bit register for signal > created at line 74. Found 1-bit register for signal > created at line 74. Found 1-bit register for signal > created at line 74. Found 1-bit register for signal > created at line 74. Found 1-bit register for signal > created at line 74. Found 1-bit register for signal > created at line 74. Found 1-bit register for signal > created at line 74. Found 1-bit register for signal > created at line 74. Found 1-bit register for signal > created at line 74. Found 1-bit register for signal > created at line 74. Found 1-bit register for signal > created at line 74. Summary: inferred 24 D-type flip-flop(s). inferred 12 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/COUNTERRegister.vhd". Found 32-bit tristate buffer for signal . Found 3-bit register for signal . Found 8-bit register for signal . Found 32-bit register for signal . Found 2-bit register for signal . Found 32-bit register for signal . Found 8-bit register for signal . Found 8-bit register for signal . Summary: inferred 93 D-type flip-flop(s). inferred 32 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/COUNTERInOutMapper.vhd". Found 1-bit xor2 for signal . Found 1-bit 16-to-1 multiplexer for signal . Found 1-bit 16-to-1 multiplexer for signal . Summary: inferred 2 Multiplexer(s). Unit synthesized. Synthesizing Unit . Related source file is "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/COUNTEREncoderDetect.vhd". Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 2 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/COUNTERStepCount.vhd". WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology. WARNING:Xst:2734 - Property "use_dsp48" is not applicable for this technology. Found 8-bit register for signal . Found 8-bit comparator equal for signal created at line 122. Found 8-bit addsub for signal created at line 112. Found 1-bit register for signal . Found 32-bit comparator less for signal created at line 149. Found 2-bit register for signal . Found 1-bit register for signal . Found 32-bit comparator lessequal for signal created at line 162. Found 32-bit register for signal . Found 32-bit addsub for signal . Found 32-bit comparator greatequal for signal created at line 149. Found 32-bit comparator greater for signal created at line 162. Found 32-bit 4-to-1 multiplexer for signal . Found 1-bit register for signal . Found 8-bit comparator not equal for signal created at line 122. Found 1-bit register for signal . Summary: inferred 46 D-type flip-flop(s). inferred 2 Adder/Subtractor(s). inferred 6 Comparator(s). inferred 32 Multiplexer(s). Unit synthesized. Synthesizing Unit . Related source file is "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/COUNTERSoftEncoder.vhd". Found 1-bit register for signal . Found 8-bit down counter for signal . Summary: inferred 1 Counter(s). inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/STEPMATCHRegister.vhd". Found 32-bit tristate buffer for signal . Found 2-bit register for signal . Found 32-bit register for signal . Found 32-bit register for signal . Summary: inferred 66 D-type flip-flop(s). inferred 32 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/STEPMATCHLogic.vhd". Found 1-bit register for signal . Found 1-bit register for signal . Found 32-bit comparator equal for signal created at line 57. Found 1-bit register for signal . Summary: inferred 3 D-type flip-flop(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/CAPTURERegister.vhd". Found 32-bit tristate buffer for signal . Found 8-bit register for signal . Found 32-bit register for signal . Found 32-bit register for signal . Summary: inferred 72 D-type flip-flop(s). inferred 32 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/CAPTUREInOutMapper.vhd". Found 1-bit register for signal . Found 1-bit xor2 for signal . Found 1-bit register for signal . Found 1-bit 16-to-1 multiplexer for signal . Found 1-bit xor2 for signal created at line 85. Summary: inferred 2 D-type flip-flop(s). inferred 1 Multiplexer(s). Unit synthesized. Synthesizing Unit . Related source file is "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/CAPTURELogic.vhd". Found 1-bit register for signal . Found 8-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 32-bit register for signal . Found 32-bit comparator greater for signal created at line 107. Found 32-bit comparator less for signal created at line 107. Found 32-bit comparator less for signal created at line 102. Summary: inferred 1 Counter(s). inferred 36 D-type flip-flop(s). inferred 3 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/READERRegister.vhd". Found 32-bit tristate buffer for signal . Found 6-bit register for signal . Found 8-bit register for signal . Found 14-bit register for signal . Found 14-bit register for signal . Found 14-bit register for signal . Found 14-bit register for signal . Found 1-bit 4-to-1 multiplexer for signal created at line 288. Found 7-bit register for signal . Found 8-bit register for signal . Found 8-bit register for signal . Found 4-bit register for signal . Found 1-bit 4-to-1 multiplexer for signal created at line 288. Found 4-bit register for signal . Found 8-bit register for signal . Found 14-bit register for signal . Found 14-bit register for signal . Found 14-bit register for signal . Found 14-bit register for signal . Summary: inferred 165 D-type flip-flop(s). inferred 2 Multiplexer(s). inferred 64 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/READERInOutMapper.vhd". Found 1-bit xor2 for signal . Found 1-bit xor2 for signal . Found 1-bit xor2 for signal . Found 1-bit xor2 for signal . Found 1-bit 16-to-1 multiplexer for signal . Found 1-bit 16-to-1 multiplexer for signal . Found 1-bit 16-to-1 multiplexer for signal . Found 1-bit 16-to-1 multiplexer for signal . Found 1-bit 16-to-1 multiplexer for signal . Found 1-bit xor2 for signal . Found 1-bit xor2 for signal . Summary: inferred 5 Multiplexer(s). Unit synthesized. Synthesizing Unit . Related source file is "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/READEREdgeDetect.vhd". Found 1-bit register for signal . Found 1-bit xor2 for signal created at line 62. Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/READERWindowDetect.vhd". Using one-hot encoding for signal . INFO:Xst:2117 - HDL ADVISOR - Mux Selector of Case statement line 117 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can: - add an 'INIT' attribute on signal (optimization is then done without any risk) - use the attribute 'signal_encoding user' to avoid onehot optimization - use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization Found 6-bit register for signal . Found 14-bit comparator equal for signal created at line 212. Found 14-bit comparator equal for signal created at line 211. Found 14-bit comparator equal for signal created at line 210. Found 14-bit comparator equal for signal created at line 209. Summary: inferred 4 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/READERCONTROLSync.vhd". Found 4-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 18 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/READERCONTROLReaderStateMachine.vhd". Using one-hot encoding for signal . INFO:Xst:2117 - HDL ADVISOR - Mux Selector of Case statement line 148 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can: - add an 'INIT' attribute on signal (optimization is then done without any risk) - use the attribute 'signal_encoding user' to avoid onehot optimization - use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization Found 1-bit register for signal . Found 1-bit register for signal . Found 19-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 4-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 11 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/READERCONTROLSpurStateMachine.vhd". Using one-hot encoding for signal . INFO:Xst:2117 - HDL ADVISOR - Mux Selector of Case statement line 110 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can: - add an 'INIT' attribute on signal (optimization is then done without any risk) - use the attribute 'signal_encoding user' to avoid onehot optimization - use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization Found 1-bit register for signal . Found 1-bit register for signal . Found 5-bit register for signal . Summary: inferred 2 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/READERMemoryAddrDataWrite.vhd". Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 10-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Counter(s). inferred 6 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/READERMemoryWriteStatemachine.vhd". INFO:Xst:1799 - State wr_0_1 is never reached in FSM . Found finite state machine for signal . ----------------------------------------------------------------------- | States | 6 | | Transitions | 7 | | Inputs | 1 | | Outputs | 3 | | Clock | INT_CLK (rising_edge) | | Reset | INT_RESET (positive) | | Reset type | asynchronous | | Reset State | wait_write_pulse | | Power Up State | wait_write_pulse | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found 9-bit register for signal . Found 15-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 24 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/READERMemoryReadThroughRAM.vhd". Found 256x16-bit dual-port RAM for signal . Found 256x16-bit dual-port RAM for signal . Found 32-bit tristate buffer for signal . Found 8-bit register for signal . Summary: inferred 2 RAM(s). inferred 8 D-type flip-flop(s). inferred 32 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/READEREncoderDetect.vhd". Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 2 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/uCINTERFACE.vhd". Unit synthesized. Synthesizing Unit . Related source file is "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/DIGITALIO.vhd". Unit synthesized. Synthesizing Unit . Related source file is "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/COUNTER.vhd". Unit synthesized. Synthesizing Unit . Related source file is "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/STEPMATCH.vhd". Unit synthesized. Synthesizing Unit . Related source file is "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/CAPTURE.vhd". Unit synthesized. Synthesizing Unit . Related source file is "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/READERCONTROL.vhd". Unit synthesized. Synthesizing Unit . Related source file is "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/READERMemory.vhd". WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:646 - Signal is assigned but never used. Unit synthesized. Synthesizing Unit . Related source file is "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/READERStepCount.vhd". Found 8-bit register for signal . Found 8-bit comparator equal for signal created at line 127. Found 8-bit addsub for signal created at line 117. Found 14-bit updown counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Counter(s). inferred 2 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/READER.vhd". Unit synthesized. Synthesizing Unit . Related source file is "//achstinf02/kohlmart/SCM_fox/KMC2600/KUSB/I-O_Flex/FPGA_01/VHDL/KUSB_IO_FLEX.vhd". WARNING:Xst:647 - Input is never used. Unit synthesized. INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing. ========================================================================= HDL Synthesis Report Macro Statistics # RAMs : 8 256x16-bit dual-port RAM : 8 # Adders/Subtractors : 4 32-bit addsub : 1 8-bit addsub : 3 # Counters : 9 10-bit up counter : 4 14-bit updown counter : 2 8-bit down counter : 1 8-bit up counter : 2 # Registers : 294 1-bit register : 204 12-bit register : 9 14-bit register : 16 15-bit register : 4 16-bit register : 1 19-bit register : 2 2-bit register : 2 3-bit register : 1 32-bit register : 10 4-bit register : 8 5-bit register : 4 6-bit register : 6 7-bit register : 2 8-bit register : 21 9-bit register : 4 # Comparators : 32 14-bit comparator equal : 16 32-bit comparator equal : 2 32-bit comparator greatequal : 1 32-bit comparator greater : 3 32-bit comparator less : 5 32-bit comparator lessequal : 1 8-bit comparator equal : 3 8-bit comparator not equal : 1 # Multiplexers : 18 1-bit 16-to-1 multiplexer : 13 1-bit 4-to-1 multiplexer : 4 32-bit 4-to-1 multiplexer : 1 # Tristates : 309 1-bit tristate buffer : 300 32-bit tristate buffer : 5 8-bit tristate buffer : 4 # Xors : 21 1-bit xor2 : 21 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Analyzing FSM for best encoding. Optimizing FSM on signal with gray encoding. Optimizing FSM on signal with gray encoding. Optimizing FSM on signal with gray encoding. Optimizing FSM on signal with gray encoding. ------------------------------ State | Encoding ------------------------------ wait_write_pulse | 000 wr_0 | 001 wr_0_1 | unreached wr_1 | 011 wr_2 | 010 wr_3 | 110 wr_4 | 111 ------------------------------ Loading device for application Rf_Device from file '3s250e.nph' in environment C:\Programme\Xilinx_92i. INFO:Xst:2737 - Unit : The RAM , combined with , will be implemented as a BLOCK RAM, absorbing the following register(s): . ----------------------------------------------------------------------- | ram_type | Block | | ----------------------------------------------------------------------- | Port A | | aspect ratio | 256-word x 16-bit | | | mode | write-first | | | clkA | connected to signal | rise | | weA | connected to signal | low | | addrA | connected to signal | | | diA | connected to signal | | | doA | connected to signal | | ----------------------------------------------------------------------- | optimisation | speed | | ----------------------------------------------------------------------- | Port B | | aspect ratio | 256-word x 16-bit | | | mode | write-first | | | clkB | connected to signal | rise | | addrB | connected to signal | | | doB | connected to signal | | ----------------------------------------------------------------------- | optimisation | speed | | ----------------------------------------------------------------------- WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . ========================================================================= Advanced HDL Synthesis Report Macro Statistics # FSMs : 1 # RAMs : 4 256x16-bit dual-port block RAM : 4 # Adders/Subtractors : 4 32-bit addsub : 1 8-bit addsub : 3 # Counters : 9 10-bit up counter : 4 14-bit updown counter : 2 8-bit down counter : 1 8-bit up counter : 2 # Registers : 1247 Flip-Flops : 1247 # Comparators : 32 14-bit comparator equal : 16 32-bit comparator equal : 2 32-bit comparator greatequal : 1 32-bit comparator greater : 3 32-bit comparator less : 5 32-bit comparator lessequal : 1 8-bit comparator equal : 3 8-bit comparator not equal : 1 # Multiplexers : 18 1-bit 16-to-1 multiplexer : 13 1-bit 4-to-1 multiplexer : 4 32-bit 4-to-1 multiplexer : 1 # Xors : 21 1-bit xor2 : 21 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= WARNING:Xst:2040 - Unit KUSB_IO_FLEX: 40 multi-source signals are replaced by logic (pull-up yes): INT_D<0>, INT_D<10>, INT_D<11>, INT_D<12>, INT_D<13>, INT_D<14>, INT_D<15>, INT_D<16>, INT_D<17>, INT_D<18>, INT_D<19>, INT_D<1>, INT_D<20>, INT_D<21>, INT_D<22>, INT_D<23>, INT_D<24>, INT_D<25>, INT_D<26>, INT_D<27>, INT_D<28>, INT_D<29>, INT_D<2>, INT_D<30>, INT_D<31>, INT_D<3>, INT_D<4>, INT_D<5>, INT_D<6>, INT_D<7>, INT_D<8>, INT_D<9>, uC_DATA<0>_MLTSRCEDGE, uC_DATA<1>_MLTSRCEDGE, uC_DATA<2>_MLT SRCEDGE, uC_DATA<3>_MLTSRCEDGE, uC_DATA<4>_MLTSRCEDGE, uC_DATA<5>_MLTSRCEDGE, uC_DATA<6>_MLTSRCEDGE, uC_DATA<7>_MLTSRCEDGE. WARNING:Xst:2042 - Unit ReadThroughRAM: 32 internal tristates are replaced by logic (pull-up yes): INT_D<0>, INT_D<10>, INT_D<11>, INT_D<12>, INT_D<13>, INT_D<14>, INT_D<15>, INT_D<16>, INT_D<17>, INT_D<18>, INT_D<19>, INT_D<1>, INT_D<20>, INT_D<21>, INT_D<22>, INT_D<23>, INT_D<24>, INT_D<25>, INT_D<26>, INT_D<27>, INT_D<28>, INT_D<29>, INT_D<2>, INT_D<30>, INT_D<31>, INT_D<3>, INT_D<4>, INT_D<5>, INT_D<6>, INT_D<7>, INT_D<8>, INT_D<9>. WARNING:Xst:2040 - Unit READERRegister: 32 multi-source signals are replaced by logic (pull-up yes): INT_D<0>, INT_D<10>, INT_D<11>, INT_D<12>, INT_D<13>, INT_D<14>, INT_D<15>, INT_D<16>, INT_D<17>, INT_D<18>, INT_D<19>, INT_D<1>, INT_D<20>, INT_D<21>, INT_D<22>, INT_D<23>, INT_D<24>, INT_D<25>, INT_D<26>, INT_D<27>, INT_D<28>, INT_D<29>, INT_D<2>, INT_D<30>, INT_D<31>, INT_D<3>, INT_D<4>, INT_D<5>, INT_D<6>, INT_D<7>, INT_D<8>, INT_D<9>. WARNING:Xst:2042 - Unit CAPTURERegister: 32 internal tristates are replaced by logic (pull-up yes): INT_D<0>, INT_D<10>, INT_D<11>, INT_D<12>, INT_D<13>, INT_D<14>, INT_D<15>, INT_D<16>, INT_D<17>, INT_D<18>, INT_D<19>, INT_D<1>, INT_D<20>, INT_D<21>, INT_D<22>, INT_D<23>, INT_D<24>, INT_D<25>, INT_D<26>, INT_D<27>, INT_D<28>, INT_D<29>, INT_D<2>, INT_D<30>, INT_D<31>, INT_D<3>, INT_D<4>, INT_D<5>, INT_D<6>, INT_D<7>, INT_D<8>, INT_D<9>. WARNING:Xst:2042 - Unit STEPMATCHRegister: 32 internal tristates are replaced by logic (pull-up yes): INT_D<0>, INT_D<10>, INT_D<11>, INT_D<12>, INT_D<13>, INT_D<14>, INT_D<15>, INT_D<16>, INT_D<17>, INT_D<18>, INT_D<19>, INT_D<1>, INT_D<20>, INT_D<21>, INT_D<22>, INT_D<23>, INT_D<24>, INT_D<25>, INT_D<26>, INT_D<27>, INT_D<28>, INT_D<29>, INT_D<2>, INT_D<30>, INT_D<31>, INT_D<3>, INT_D<4>, INT_D<5>, INT_D<6>, INT_D<7>, INT_D<8>, INT_D<9>. WARNING:Xst:2042 - Unit COUNTERRegister: 32 internal tristates are replaced by logic (pull-up yes): INT_D<0>, INT_D<10>, INT_D<11>, INT_D<12>, INT_D<13>, INT_D<14>, INT_D<15>, INT_D<16>, INT_D<17>, INT_D<18>, INT_D<19>, INT_D<1>, INT_D<20>, INT_D<21>, INT_D<22>, INT_D<23>, INT_D<24>, INT_D<25>, INT_D<26>, INT_D<27>, INT_D<28>, INT_D<29>, INT_D<2>, INT_D<30>, INT_D<31>, INT_D<3>, INT_D<4>, INT_D<5>, INT_D<6>, INT_D<7>, INT_D<8>, INT_D<9>. WARNING:Xst:2042 - Unit DIGITALIORegister: 32 internal tristates are replaced by logic (pull-up yes): INT_D<0>, INT_D<10>, INT_D<11>, INT_D<12>, INT_D<13>, INT_D<14>, INT_D<15>, INT_D<16>, INT_D<17>, INT_D<18>, INT_D<19>, INT_D<1>, INT_D<20>, INT_D<21>, INT_D<22>, INT_D<23>, INT_D<24>, INT_D<25>, INT_D<26>, INT_D<27>, INT_D<28>, INT_D<29>, INT_D<2>, INT_D<30>, INT_D<31>, INT_D<3>, INT_D<4>, INT_D<5>, INT_D<6>, INT_D<7>, INT_D<8>, INT_D<9>. WARNING:Xst:2042 - Unit uCINTERFACERegister: 32 internal tristates are replaced by logic (pull-up yes): INT_D<0>, INT_D<10>, INT_D<11>, INT_D<12>, INT_D<13>, INT_D<14>, INT_D<15>, INT_D<16>, INT_D<17>, INT_D<18>, INT_D<19>, INT_D<1>, INT_D<20>, INT_D<21>, INT_D<22>, INT_D<23>, INT_D<24>, INT_D<25>, INT_D<26>, INT_D<27>, INT_D<28>, INT_D<29>, INT_D<2>, INT_D<30>, INT_D<31>, INT_D<3>, INT_D<4>, INT_D<5>, INT_D<6>, INT_D<7>, INT_D<8>, INT_D<9>. WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Mapping all equations... Building and optimizing final netlist ... INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : Found area constraint ratio of 100 (+ 5) on block KUSB_IO_FLEX, actual ratio is 66. INFO:Xst:2260 - The FF/Latch > in Unit is equivalent to the following 11 FFs/Latches : > > > > > > > > > > > INFO:Xst:1843 - HDL ADVISOR - FlipFlop myCLOCKManager/RESET_out connected to a primary input has been replicated FlipFlop myCLOCKManager/RESET_out has been replicated 2 time(s) INFO:Xst:1843 - HDL ADVISOR - FlipFlop myCLOCKManager/RESET_out connected to a primary input has been replicated FlipFlop myuCINTERFACE/myuCINTERFACESync/INT_A_sig_2 has been replicated 1 time(s) INFO:Xst:1843 - HDL ADVISOR - FlipFlop myuCINTERFACE/myuCINTERFACESync/INT_A_sig_2 connected to a primary input has been replicated FlipFlop myuCINTERFACE/myuCINTERFACESync/INT_A_sig_3 has been replicated 1 time(s) INFO:Xst:1843 - HDL ADVISOR - FlipFlop myuCINTERFACE/myuCINTERFACESync/INT_A_sig_3 connected to a primary input has been replicated FlipFlop myuCINTERFACE/myuCINTERFACESync/INT_nCS has been replicated 1 time(s) INFO:Xst:1843 - HDL ADVISOR - FlipFlop myuCINTERFACE/myuCINTERFACESync/INT_nCS connected to a primary input has been replicated Final Macro Processing ... ========================================================================= Final Register Report Macro Statistics # Registers : 1356 Flip-Flops : 1356 ========================================================================= ========================================================================= * Partition Report * ========================================================================= Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- ========================================================================= * Final Report * ========================================================================= Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ uC_CLK | BUFGP | 1360 | -----------------------------------+------------------------+-------+ Asynchronous Control Signals Information: ---------------------------------------- -------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+-------+ Control Signal | Buffer(FF name) | Load | -------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+-------+ myCLOCKManager/RESET_out_2(myCLOCKManager/RESET_out_2:Q) | NONE(myREADER1/myREADERControl/myREADERCONTROLSpurStatemachine_A/current_state_2)| 424 | myCLOCKManager/RESET_out_1(myCLOCKManager/RESET_out_1:Q) | NONE(myREADER2/myREADERRegister/WINDOW_START_A_sig_9) | 425 | myCLOCKManager/RESET_out(myCLOCKManager/RESET_out:Q) | NONE(myCAPTURE/myCAPTURERegister/CAPTURE_WINDOW_END_sig_2) | 395 | myREADER1/myREADERStepCount/COUNT_PRESCALER_var_2__and0001(myREADER1/myREADERStepCount/COUNT_PRESCALER_var_2__and00011:O)| NONE(myREADER1/myREADERStepCount/COUNT_PRESCALER_var_2) | 1 | myREADER1/myREADERStepCount/COUNT_PRESCALER_var_2__and0002(myREADER1/myREADERStepCount/COUNT_PRESCALER_var_2__and00021:O)| NONE(myREADER1/myREADERStepCount/COUNT_PRESCALER_var_2) | 1 | myREADER1/myREADERStepCount/COUNT_PRESCALER_var_7__and0001(myREADER1/myREADERStepCount/COUNT_PRESCALER_var_7__and00011:O)| NONE(myREADER1/myREADERStepCount/COUNT_PRESCALER_var_7) | 1 | myREADER1/myREADERStepCount/COUNT_PRESCALER_var_7__and0002(myREADER1/myREADERStepCount/COUNT_PRESCALER_var_7__and00021:O)| NONE(myREADER1/myREADERStepCount/COUNT_PRESCALER_var_7) | 1 | myREADER2/myREADERStepCount/COUNT_PRESCALER_var_0__and0001(myREADER2/myREADERStepCount/COUNT_PRESCALER_var_0__and00011:O)| NONE(myREADER2/myREADERStepCount/COUNT_PRESCALER_var_0) | 1 | myREADER2/myREADERStepCount/COUNT_PRESCALER_var_0__and0002(myREADER2/myREADERStepCount/COUNT_PRESCALER_var_0__and00021:O)| NONE(myREADER2/myREADERStepCount/COUNT_PRESCALER_var_0) | 1 | myREADER1/myREADERStepCount/COUNT_PRESCALER_var_5__and0001(myREADER1/myREADERStepCount/COUNT_PRESCALER_var_5__and00011:O)| NONE(myREADER1/myREADERStepCount/COUNT_PRESCALER_var_5) | 1 | myREADER1/myREADERStepCount/COUNT_PRESCALER_var_5__and0002(myREADER1/myREADERStepCount/COUNT_PRESCALER_var_5__and00021:O)| NONE(myREADER1/myREADERStepCount/COUNT_PRESCALER_var_5) | 1 | myREADER1/myREADERStepCount/COUNT_PRESCALER_var_6__and0001(myREADER1/myREADERStepCount/COUNT_PRESCALER_var_6__and00011:O)| NONE(myREADER1/myREADERStepCount/COUNT_PRESCALER_var_6) | 1 | myREADER1/myREADERStepCount/COUNT_PRESCALER_var_6__and0002(myREADER1/myREADERStepCount/COUNT_PRESCALER_var_6__and00021:O)| NONE(myREADER1/myREADERStepCount/COUNT_PRESCALER_var_6) | 1 | myREADER1/myREADERStepCount/COUNT_PRESCALER_var_0__and0001(myREADER1/myREADERStepCount/COUNT_PRESCALER_var_0__and00011:O)| NONE(myREADER1/myREADERStepCount/COUNT_PRESCALER_var_0) | 1 | myREADER1/myREADERStepCount/COUNT_PRESCALER_var_0__and0002(myREADER1/myREADERStepCount/COUNT_PRESCALER_var_0__and00021:O)| NONE(myREADER1/myREADERStepCount/COUNT_PRESCALER_var_0) | 1 | myREADER2/myREADERStepCount/COUNT_PRESCALER_var_4__and0001(myREADER2/myREADERStepCount/COUNT_PRESCALER_var_4__and00011:O)| NONE(myREADER2/myREADERStepCount/COUNT_PRESCALER_var_4) | 1 | myREADER2/myREADERStepCount/COUNT_PRESCALER_var_4__and0002(myREADER2/myREADERStepCount/COUNT_PRESCALER_var_4__and00021:O)| NONE(myREADER2/myREADERStepCount/COUNT_PRESCALER_var_4) | 1 | myREADER2/myREADERStepCount/COUNT_PRESCALER_var_3__and0001(myREADER2/myREADERStepCount/COUNT_PRESCALER_var_3__and00011:O)| NONE(myREADER2/myREADERStepCount/COUNT_PRESCALER_var_3) | 1 | myREADER2/myREADERStepCount/COUNT_PRESCALER_var_3__and0002(myREADER2/myREADERStepCount/COUNT_PRESCALER_var_3__and00021:O)| NONE(myREADER2/myREADERStepCount/COUNT_PRESCALER_var_3) | 1 | myREADER2/myREADERStepCount/COUNT_PRESCALER_var_5__and0001(myREADER2/myREADERStepCount/COUNT_PRESCALER_var_5__and00011:O)| NONE(myREADER2/myREADERStepCount/COUNT_PRESCALER_var_5) | 1 | myREADER2/myREADERStepCount/COUNT_PRESCALER_var_5__and0002(myREADER2/myREADERStepCount/COUNT_PRESCALER_var_5__and00021:O)| NONE(myREADER2/myREADERStepCount/COUNT_PRESCALER_var_5) | 1 | myREADER2/myREADERStepCount/COUNT_PRESCALER_var_7__and0001(myREADER2/myREADERStepCount/COUNT_PRESCALER_var_7__and00011:O)| NONE(myREADER2/myREADERStepCount/COUNT_PRESCALER_var_7) | 1 | myREADER2/myREADERStepCount/COUNT_PRESCALER_var_7__and0002(myREADER2/myREADERStepCount/COUNT_PRESCALER_var_7__and00021:O)| NONE(myREADER2/myREADERStepCount/COUNT_PRESCALER_var_7) | 1 | myREADER2/myREADERStepCount/COUNT_PRESCALER_var_6__and0001(myREADER2/myREADERStepCount/COUNT_PRESCALER_var_6__and00011:O)| NONE(myREADER2/myREADERStepCount/COUNT_PRESCALER_var_6) | 1 | myREADER2/myREADERStepCount/COUNT_PRESCALER_var_6__and0002(myREADER2/myREADERStepCount/COUNT_PRESCALER_var_6__and00021:O)| NONE(myREADER2/myREADERStepCount/COUNT_PRESCALER_var_6) | 1 | myREADER2/myREADERStepCount/COUNT_PRESCALER_var_2__and0001(myREADER2/myREADERStepCount/COUNT_PRESCALER_var_2__and00011:O)| NONE(myREADER2/myREADERStepCount/COUNT_PRESCALER_var_2) | 1 | myREADER2/myREADERStepCount/COUNT_PRESCALER_var_2__and0002(myREADER2/myREADERStepCount/COUNT_PRESCALER_var_2__and00021:O)| NONE(myREADER2/myREADERStepCount/COUNT_PRESCALER_var_2) | 1 | myREADER2/myREADERStepCount/COUNT_PRESCALER_var_1__and0001(myREADER2/myREADERStepCount/COUNT_PRESCALER_var_1__and00011:O)| NONE(myREADER2/myREADERStepCount/COUNT_PRESCALER_var_1) | 1 | myREADER2/myREADERStepCount/COUNT_PRESCALER_var_1__and0002(myREADER2/myREADERStepCount/COUNT_PRESCALER_var_1__and00021:O)| NONE(myREADER2/myREADERStepCount/COUNT_PRESCALER_var_1) | 1 | myREADER1/myREADERStepCount/COUNT_PRESCALER_var_3__and0001(myREADER1/myREADERStepCount/COUNT_PRESCALER_var_3__and00011:O)| NONE(myREADER1/myREADERStepCount/COUNT_PRESCALER_var_3) | 1 | myREADER1/myREADERStepCount/COUNT_PRESCALER_var_3__and0002(myREADER1/myREADERStepCount/COUNT_PRESCALER_var_3__and00021:O)| NONE(myREADER1/myREADERStepCount/COUNT_PRESCALER_var_3) | 1 | myREADER1/myREADERStepCount/COUNT_PRESCALER_var_4__and0001(myREADER1/myREADERStepCount/COUNT_PRESCALER_var_4__and00011:O)| NONE(myREADER1/myREADERStepCount/COUNT_PRESCALER_var_4) | 1 | myREADER1/myREADERStepCount/COUNT_PRESCALER_var_4__and0002(myREADER1/myREADERStepCount/COUNT_PRESCALER_var_4__and00021:O)| NONE(myREADER1/myREADERStepCount/COUNT_PRESCALER_var_4) | 1 | myREADER1/myREADERStepCount/COUNT_PRESCALER_var_1__and0001(myREADER1/myREADERStepCount/COUNT_PRESCALER_var_1__and00011:O)| NONE(myREADER1/myREADERStepCount/COUNT_PRESCALER_var_1) | 1 | myREADER1/myREADERStepCount/COUNT_PRESCALER_var_1__and0002(myREADER1/myREADERStepCount/COUNT_PRESCALER_var_1__and00021:O)| NONE(myREADER1/myREADERStepCount/COUNT_PRESCALER_var_1) | 1 | -------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+-------+ Timing Summary: --------------- Speed Grade: -5 Minimum period: 10.364ns (Maximum Frequency: 96.488MHz) Minimum input arrival time before clock: 2.700ns Maximum output required time after clock: 9.727ns Maximum combinational path delay: 8.420ns ========================================================================= Process "Synthesize" completed successfully Started : "Launching RTL Schematic Viewer for KUSB_IO_FLEX.ngr".