#include <asf.h>
#include <stdint.h>


static void hse(void)
{
	/*XOSC INIT*/
	uint8_t to=0;
	MCLK->APBAMASK.reg |= MCLK_APBAMASK_OSCCTRL;          /*enable peripheral clock for OSCC*/ 
	OSCCTRL->XOSCCTRL.reg &=~ OSCCTRL_XOSCCTRL_ONDEMAND;  /*set XOSC to always on*/
	OSCCTRL->XOSCCTRL.reg |= (OSCCTRL_XOSCCTRL_ENABLE|OSCCTRL_XOSCCTRL_XTALEN| 
  OSCCTRL_XOSCCTRL_AMPGC|OSCCTRL_XOSCCTRL_RUNSTDBY);    /*enable XTAL, XOSC, automatic gain, set XOSC to  run in standby*/
	OSCCTRL->XOSCCTRL.reg |= (3<<8);                      /*set XOSC gain to 16Mhz*/
	while((OSCCTRL->STATUS.reg&OSCCTRL_STATUS_XOSCRDY)==0)/*wait until XOSC is ready*/
	{
	 to++;
	 if(to>254)
		{
			break;
		}
	}
	 to = 0;
 
	/*Clock switch*/
	 GCLK->GENCTRL[0].reg  &= ((~GCLK_GENCTRL_SRC_Msk)|0x00);   /*switch clock to XOSC*/
	while((GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL_GCLK0)!=0)/*wait until clock is switched*/
	{
		to++;
		if(to>254)
		{
			break;
		}
	}
	to = 0;
	/*PLL INIT*/
	OSCCTRL->DPLLCTRLA.reg &= (~OSCCTRL_DPLLCTRLA_ONDEMAND);          /*set pll to always on*/
	OSCCTRL->DPLLCTRLB.reg |= (OSCCTRL_DPLLCTRLB_LTIME(0x4));         /*set locktime to 8ms*/
	OSCCTRL->DPLLCTRLB.reg &= (~OSCCTRL_DPLLCTRLB_REFCLK_Msk);        /*clear refclock register*/
	OSCCTRL->DPLLCTRLB.reg |= (OSCCTRL_DPLLCTRLB_DIV(0x5));           /*set XOSC predivisor to 5 ->(12Mhz/((5+1)*2)=1Mhz)*/
	OSCCTRL->DPLLCTRLB.reg |= (OSCCTRL_DPLLCTRLB_REFCLK(1));          /*set XOSC as refclock*/
	OSCCTRL->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ENABLE;               /*enable pll*/
	while((OSCCTRL->DPLLSYNCBUSY.reg&OSCCTRL_DPLLSYNCBUSY_ENABLE)!=0)	/*wait until pll is enabled*/
	{
		to++;
		if(to>254)
		{
			break;
		}
	}
	to = 0;
 
	OSCCTRL->DPLLRATIO.reg |= (OSCCTRL_DPLLRATIO_LDR(0x2f));              /*set divisor to 47 (48*1Mhz=48Mhz)*/
	while((OSCCTRL->DPLLSYNCBUSY.reg&OSCCTRL_DPLLSYNCBUSY_DPLLRATIO)!=0)  /*wait until divisor register is synchronized*/
	{
		to++;
		if(to>254)
		{
			to=0;
			break;
		}
	}
	to = 0;
 
	while ((OSCCTRL->DPLLSTATUS.reg&OSCCTRL_DPLLSTATUS_LOCK)==0)        /*wait until pll is locked*/
	{
		to++;
		if(to>254)
		{
			break;
		}
	}
	while((OSCCTRL->DPLLSTATUS.reg &OSCCTRL_DPLLSTATUS_CLKRDY)==0)      /*wait until clock is ready*/
	{
	 
	}
	to = 0;

	/*Clock Switch*/
	GCLK->GENCTRL[0].reg &=((~GCLK_GENCTRL_SRC_Msk)|0x07);              /*set DPLL96 as source for CLKGEN0*/
	while((GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL_GCLK0)!=0)        /*wait until CLKGEN0 is synchronized*/
	{
		to++;
		if(to>254)
		{
			break;
		}
	}
	to = 0;
 
}