---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 10:04:14 10/24/2007 -- Design Name: -- Module Name: test_multiplexer - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity test_multiplexer is Port ( S0 : in STD_LOGIC; E0 : in STD_LOGIC; E1 : in STD_LOGIC; CLK : in STD_LOGIC; LED : out STD_LOGIC); end test_multiplexer; architecture Behavioral of test_multiplexer is begin process (S0, E0, E1) begin if CLK'event and CLK='1' then if S0 = '0' then LED <= E0; else LED <= E1; end if; end if; end process; end Behavioral;