| Offset | Field | Description |
|---|---|---|
| 0x0 | SMC2_CSR[8] (SMC2_CSR) | SMC2 Chip Select Register |
| Offset | Name | Description | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 6..0 | SMC2_NWS AT91C_SMC2_NWS | Number of Wait States This field defines the Read and Write signal pulse length from 1 cycle up to 128 cycles. | |||||||||||||||
| 7 | SMC2_WSEN AT91C_SMC2_WSEN | Wait State Enable 0 = Wait States are disabled. 1 = Wait States are enabled. | |||||||||||||||
| 11..8 | SMC2_TDF AT91C_SMC2_TDF | Data Float Time The external bus is marked occupied and cannot be used by another chip select during TDF cycle. Up to 15 cycles can be defined. | |||||||||||||||
| 12 | SMC2_BAT AT91C_SMC2_BAT | Byte Access Type This field is used only if DBW defines a 16- or 32-bit data bus. 0 = Chip Select line is connected to two 8-bit wide devices or four 8-bit devices. 1 = Chip Select line is connected to a 16-bit wide device. | |||||||||||||||
| 13 | SMC2_DBW AT91C_SMC2_DBW | Data Bus Width
| |||||||||||||||
| 15 | SMC2_DRP AT91C_SMC2_DRP | Data Read Protocol 0 = Standard Read Protocol is used. 1 = Early Read Protocol is used. | |||||||||||||||
| 17..16 | SMC2_ACSS AT91C_SMC2_ACSS | Address to Chip Select Setup
| |||||||||||||||
| 26..24 | SMC2_RWSETUP AT91C_SMC2_RWSETUP | Read and Write Signal Setup Time | |||||||||||||||
| 30..28 | SMC2_RWHOLD AT91C_SMC2_RWHOLD | Read and Write Signal Hold Time |