| Periph ID AIC | Symbol | Description |
|---|---|---|
| 1 | (AT91C_ID_SYS) | System Peripheral |
| Function | Description |
|---|---|
| AT91F_MC_CfgPMC | Enable Peripheral clock in PMC for MC |
| Offset | Field | Description |
|---|---|---|
| 0x0 | MC_RCR | MC Remap Control Register |
| 0x4 | MC_ASR | MC Abort Status Register |
| 0x8 | MC_AASR | MC Abort Address Status Register |
| 0x10 | MC_PUIA[16] (MC_PUIA) | MC Protection Unit Area |
| 0x50 | MC_PUP | MC Protection Unit Peripherals |
| 0x54 | MC_PUER | MC Protection Unit Enable Register |
| 0x60 | MC0_FMR (MC_FMR) | MC Flash Mode Register |
| 0x64 | MC0_FCR (MC_FCR) | MC Flash Command Register |
| 0x68 | MC0_FSR (MC_FSR) | MC Flash Status Register |
| 0x6C | MC0_VR (EFC_VR) | MC Flash Version Register |
| 0x70 | MC1_FMR (MC_FMR) | MC Flash Mode Register |
| 0x74 | MC1_FCR (MC_FCR) | MC Flash Command Register |
| 0x78 | MC1_FSR (MC_FSR) | MC Flash Status Register |
| 0x7C | MC1_VR (EFC_VR) | MC Flash Version Register |
| Function | Description |
|---|---|
| AT91F_MC_EFC0_PerformCmd | Perform EFC Command |
| AT91F_MC_EFC0_GetModeReg | Return MC EFC Mode Regsiter |
| AT91F_MC_EFC1_CfgModeReg | Configure the EFC Mode Register of the MC controller |
| AT91F_MC_EFC0_IsInterruptMasked | Test if EFC MC Interrupt is Masked |
| AT91F_MC_EFC1_GetStatus | Return MC EFC Status |
| AT91F_MC_EFC0_CfgModeReg | Configure the EFC Mode Register of the MC controller |
| AT91F_MC_EFC1_IsInterruptMasked | Test if EFC MC Interrupt is Masked |
| AT91F_MC_EFC1_IsInterruptSet | Test if EFC MC Interrupt is Set |
| AT91F_MC_EFC1_GetModeReg | Return MC EFC Mode Regsiter |
| AT91F_MC_EFC_ComputeFMCN | Return MC EFC Mode Regsiter |
| AT91F_MC_EFC0_IsInterruptSet | Test if EFC MC Interrupt is Set |
| AT91F_MC_EFC1_PerformCmd | Perform EFC Command |
| AT91F_MC_Remap | Make Remap |
| AT91F_MC_EFC0_GetStatus | Return MC EFC Status |
| Offset | Name | Description |
|---|---|---|
| 0 | MC_RCB AT91C_MC_RCB | Remap Command Bit 0: No effect. 1: This Command Bit acts on a toggle basis: writing a 1 alternatively cancels and restores the remapping of the page zero memory devices. |
| Offset | Name | Description | ||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0 | MC_UNDADD AT91C_MC_UNDADD | Undefined Addess Abort Status 0: The last abort is not due to the access of an undefined address in the address space. 1: The last abort is due to the access of an undefined address in the address space. | ||||||||||||
| 1 | MC_MISADD AT91C_MC_MISADD | Misaligned Addess Abort Status 0: During the last aborted access, the address was not unaligned. 1: During the last aborted access, the address was unaligned. | ||||||||||||
| 2 | MC_MPU AT91C_MC_MPU | Memory protection Unit Abort Status 0: The last abort is not due to the MPU. 1: The last abort is due to the MPU. | ||||||||||||
| 9..8 | MC_ABTSZ AT91C_MC_ABTSZ | Abort Size Status This field gives the size of the aborted access of the current master.
| ||||||||||||
| 11..10 | MC_ABTTYP AT91C_MC_ABTTYP | Abort Type Status This field gives the type of the aborted access of the current master.
| ||||||||||||
| 16 | MC_MST0 AT91C_MC_MST0 | Master 0 Abort Source 0: The last abort was not due to the Master 0. 1: The last abort was due to the Master 0. | ||||||||||||
| 17 | MC_MST1 AT91C_MC_MST1 | Master 1 Abort Source 0: The last abort was not due to the Master 1. 1: The last abort was due to the Master 1. | ||||||||||||
| 24 | MC_SVMST0 AT91C_MC_SVMST0 | Saved Master 0 Abort Source 0: No abort due to the Master 0 occurred since the last read of MC_ASR or it is notified in the bit MST0. 1: At least one abort due to the Master 0 occurred since the last read of MC_ASR. | ||||||||||||
| 25 | MC_SVMST1 AT91C_MC_SVMST1 | Saved Master 1 Abort Source 0: No abort due to the Master 1 occurred since the last read of MC_ASR or it is notified in the bit MST1. 1: At least one abort due to the Master 1 occurred since the last read of MC_ASR. |
| Offset | Name | Description | |||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1..0 | MC_PROT AT91C_MC_PROT | Protection The area protection mode is defined as per the following table:
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| 7..4 | MC_SIZE AT91C_MC_SIZE | Internal Area Size
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| 27..10 | MC_BA AT91C_MC_BA | Internal Area Base Address These bits define the Base Address of the area. Note that the Area Base Address must be aligned with respect to the size of that area. |
| Offset | Name | Description | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1..0 | MC_PROT AT91C_MC_PROT | Protection The area protection mode is defined as per the following table:
|
| Offset | Name | Description |
|---|---|---|
| 0 | MC_PUEB AT91C_MC_PUEB | Protection Unit enable Bit 0: The Memory Controller Protection Unit is disabled. 1: The Memory Controller Protection Unit is enabled. |