| Signal | Symbol | PIO controller | Description |
|---|---|---|---|
| PWM3 | (AT91C_PB14_PWM3 ) | PIOB Periph: A Bit: 14 | |
| PWM3 | (AT91C_PB7_PWM3 ) | PIOB Periph: A Bit: 7 |
| Function | Description |
|---|---|
| AT91F_PWMC_CH3_CfgPIO | Configure PIO controllers to drive PWMC_CH3 signals |
| Signal | Symbol | PIO controller | Description |
|---|---|---|---|
| PWM2 | (AT91C_PB13_PWM2 ) | PIOB Periph: A Bit: 13 | |
| PWM2 | (AT91C_PB25_PWM2 ) | PIOB Periph: A Bit: 25 | |
| PWM2 | (AT91C_PA2_PWM2 ) | PIOA Periph: A Bit: 2 |
| Function | Description |
|---|---|
| AT91F_PWMC_CH2_CfgPIO | Configure PIO controllers to drive PWMC_CH2 signals |
| Signal | Symbol | PIO controller | Description |
|---|---|---|---|
| PWM1 | (AT91C_PB12_PWM1 ) | PIOB Periph: A Bit: 12 | |
| PWM1 | (AT91C_PB24_PWM1 ) | PIOB Periph: A Bit: 24 | |
| PWM1 | (AT91C_PA1_PWM1 ) | PIOA Periph: A Bit: 1 |
| Function | Description |
|---|---|
| AT91F_PWMC_CH1_CfgPIO | Configure PIO controllers to drive PWMC_CH1 signals |
| Signal | Symbol | PIO controller | Description |
|---|---|---|---|
| PWM0 | (AT91C_PB11_PWM0 ) | PIOB Periph: A Bit: 11 | |
| PWM0 | (AT91C_PB23_PWM0 ) | PIOB Periph: A Bit: 23 | |
| PWM0 | (AT91C_PA0_PWM0 ) | PIOA Periph: A Bit: 0 |
| Function | Description |
|---|---|
| AT91F_PWMC_CH0_CfgPIO | Configure PIO controllers to drive PWMC_CH0 signals |
| Offset | Field | Description |
|---|---|---|
| 0x0 | PWMC_CMR | Channel Mode Register |
| 0x4 | PWMC_CDTYR | Channel Duty Cycle Register |
| 0x8 | PWMC_CPRDR | Channel Period Register |
| 0xC | PWMC_CCNTR | Channel Counter Register |
| 0x10 | PWMC_CUPDR | Channel Update Register |
| 0x14 | PWMC_Reserved[3] (PWMC_RESERVED) | Reserved |
| Offset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 3..0 | PWMC_CPRE AT91C_PWMC_CPRE | Channel Pre-scaler : PWMC_CLKx
| ||||||||||||||||||||||||||||||||||||||||||
| 8 | PWMC_CALG AT91C_PWMC_CALG | Channel Alignment 0: The period is left aligned. 1: The period is center aligned. | ||||||||||||||||||||||||||||||||||||||||||
| 9 | PWMC_CPOL AT91C_PWMC_CPOL | Channel Polarity 0: The period starts by a low level. 1: The period starts by a high level. | ||||||||||||||||||||||||||||||||||||||||||
| 10 | PWMC_CPD AT91C_PWMC_CPD | Channel Update Period 0: Writting to the PWMC_CUPDx will notify the duty cycle at the next period start event. 1: Writting to the PWMC_CUPDx will notify the period at the next period start event. |
| Offset | Name | Description |
|---|---|---|
| 31..0 | PWMC_CDTY AT91C_PWMC_CDTY | Channel Duty Cycle Defines the waveform duty cycle. THis value must be defined between 0 and CPRD(PWMC_CPRx). |
| Offset | Name | Description |
|---|---|---|
| 31..0 | PWMC_CPRD AT91C_PWMC_CPRD | Channel Period If the waveform is left aligned, its period is CPRD*TMCK. If the waveform is center aligned, its period is 2*CPRD*TMCK. |
| Offset | Name | Description |
|---|---|---|
| 31..0 | PWMC_CCNT AT91C_PWMC_CCNT | Channel Counter Internal Counter Value. |
| Offset | Name | Description |
|---|---|---|
| 31..0 | PWMC_CUPD AT91C_PWMC_CUPD | Channel Update This register is a double buffer for the period or the duty cycle (CUP in PWMC_CMRx). It prevents from unexpected waveform when modifying waveform period or duty cycle. |