| Periph ID AIC | Symbol | Description |
|---|---|---|
| 9 | (AT91C_ID_TWI) | Two-Wire Interface |
| Signal | Symbol | PIO controller | Description |
|---|---|---|---|
| TWD | (AT91C_PA3_TWD ) | PIOA Periph: A Bit: 3 | |
| TWCK | (AT91C_PA4_TWCK ) | PIOA Periph: A Bit: 4 |
| Function | Description |
|---|---|
| AT91F_TWI_CfgPIO | Configure PIO controllers to drive TWI signals |
| AT91F_TWI_CfgPMC | Enable Peripheral clock in PMC for TWI |
| Offset | Field | Description |
|---|---|---|
| 0x0 | TWI_CR | Control Register |
| 0x4 | TWI_MMR | Master Mode Register |
| 0x8 | TWI_SMR | Slave Mode Register |
| 0xC | TWI_IADR | Internal Address Register |
| 0x10 | TWI_CWGR | Clock Waveform Generator Register |
| 0x20 | TWI_SR | Status Register |
| 0x24 | TWI_IER | Interrupt Enable Register |
| 0x28 | TWI_IDR | Interrupt Disable Register |
| 0x2C | TWI_IMR | Interrupt Mask Register |
| 0x30 | TWI_RHR | Receive Holding Register |
| 0x34 | TWI_THR | Transmit Holding Register |
| 0x100 | TWI_RPR (PDC_RPR) | Receive Pointer Register |
| 0x104 | TWI_RCR (PDC_RCR) | Receive Counter Register |
| 0x108 | TWI_TPR (PDC_TPR) | Transmit Pointer Register |
| 0x10C | TWI_TCR (PDC_TCR) | Transmit Counter Register |
| 0x110 | TWI_RNPR (PDC_RNPR) | Receive Next Pointer Register |
| 0x114 | TWI_RNCR (PDC_RNCR) | Receive Next Counter Register |
| 0x118 | TWI_TNPR (PDC_TNPR) | Transmit Next Pointer Register |
| 0x11C | TWI_TNCR (PDC_TNCR) | Transmit Next Counter Register |
| 0x120 | TWI_PTCR (PDC_PTCR) | PDC Transfer Control Register |
| 0x124 | TWI_PTSR (PDC_PTSR) | PDC Transfer Status Register |
| Function | Description |
|---|---|
| AT91F_TWI_EnableIt | Enable TWI IT |
| AT91F_TWI_DisableIt | Disable TWI IT |
| AT91F_TWI_GetInterruptMaskStatus | Return TWI Interrupt Mask Status |
| AT91F_TWI_IsInterruptMasked | Test if TWI Interrupt is Masked |
| AT91F_TWI_Configure | Configure TWI in master mode |
| Offset | Name | Description |
|---|---|---|
| 0 | TWI_START AT91C_TWI_START | Send a START Condition 0: No effect. 1: A frame beginning with a START bit is transmitted according to the features defined in the mode register. This action is necessary when the TWI peripheral wants to read data from a slave. When configured in master mode with a write operation, a frame is sent with the mode register as soon as the user writes a character in the holding register. |
| 1 | TWI_STOP AT91C_TWI_STOP | Send a STOP Condition 0: No effect. 1: STOP Condition is sent just after completing the current byte transmission in master read or write mode. In single data byte master read or write, the START and STOP must both be set. In multiple data bytes master read or write, the STOP must be set before ACK/NACK bit transmission. In master read mode, if a NACK bit is received, the STOP is automatically performed. In multiple data write operation, when both THR and shift register are empty, a STOP condition is automatically sent. |
| 2 | TWI_MSEN AT91C_TWI_MSEN | TWI Master Transfer Enabled 0: No effect. 1: If MSDIS = 0, the master data transfer is enabled. |
| 3 | TWI_MSDIS AT91C_TWI_MSDIS | TWI Master Transfer Disabled 0: No effect. 1: The master data transfer is disabled, all pending data is transmitted. The shifter and holding character (if it contains data) are transmitted in case of write operation. In read operation, the character being transferred must be completely received before disabling. |
| 4 | TWI_SVEN AT91C_TWI_SVEN | TWI Slave mode Enabled 0: No effect. 1: If SVEN = 1, the slave mode is enabled. |
| 5 | TWI_SVDIS AT91C_TWI_SVDIS | TWI Slave mode Disabled 0: No effect. 1: If SVDIS = 1, The slave mode is disabled. The shifter and holding characters (if it contains data) are transmitted in case of read operation. In write operation, the character being transferred must be completely received before disabling. |
| 7 | TWI_SWRST AT91C_TWI_SWRST | Software Reset 0: No effect. 1: Equivalent to a system reset. |
| Offset | Name | Description | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 9..8 | TWI_IADRSZ AT91C_TWI_IADRSZ | Internal Device Address Size
| |||||||||||||||
| 12 | TWI_MREAD AT91C_TWI_MREAD | Master Read Direction 0: Master write direction 1: Master read direction | |||||||||||||||
| 22..16 | TWI_DADR AT91C_TWI_DADR | Device Address The device address is used in master mode to access slave devices in read or write mode. |
| Offset | Name | Description |
|---|---|---|
| 22..16 | TWI_SADR AT91C_TWI_SADR | Slave Address The slave device address is used in order to be accessed by master devices in read or write mode. SADR has to be programmed before enabling the Slave mode or after a general call. |
| Offset | Name | Description |
|---|---|---|
| 7..0 | TWI_CLDIV AT91C_TWI_CLDIV | Clock Low Divider The SCL low period is defined as follows: Tlow = (CLDIV * 2 ^CKDIV) + 4) * Tmclk |
| 15..8 | TWI_CHDIV AT91C_TWI_CHDIV | Clock High Divider The SCL high period is defined as follows: Thigh = (CLDIV * 2 ^CKDIV) + 4) * Tmclk |
| 18..16 | TWI_CKDIV AT91C_TWI_CKDIV | Clock Divider The CKDIV is used to increase both SCL high and low periods. |
| Offset | Name | Description |
|---|---|---|
| 0 slave | TWI_TXCOMP_SLAVE AT91C_TWI_TXCOMP_SLAVE | Transmission Completed 0: As soon as a Start is detected. 1: After a Stop or a Repeated Start + an address different from SADR is detected. |
| 1 slave | TWI_RXRDY AT91C_TWI_RXRDY | Receive holding register ReaDY 0: No character has been received since the last TWI_RHR read operation. 1: A byte has been received in the TWI_RHR since the last read. |
| 2 slave | TWI_TXRDY_SLAVE AT91C_TWI_TXRDY_SLAVE | Transmit holding register ReaDY 0: As soon as a data is written in the TWI_THR, until this data has been transmitted and acknowledged (ACK or NACK). 1: It indicates that the TWI_THR is empty and that a data has been transmitted and acknowledged. If TXRDY is high and if a NACK has been detected, it means that the transmission will be stopped. Thus when TRDY = NACK = 1, the programmer must not fill TWI_THR to avoid loosing it. |
| 3 slave | TWI_SVREAD AT91C_TWI_SVREAD | Slave READ (used only in Slave mode) When SVACC is low SVREAD is irrelevant. 0: Indicates that a write access is performed by a Master. 1: Indicates that a read access is performed by a Master. |
| 4 slave | TWI_SVACC AT91C_TWI_SVACC | Slave ACCess (used only in Slave mode) 0: TWI isnt addressed. SVACC is automatically cleared after a NACK or a STOP condition is detected. 1: Indicates that the address decoding sequence has matched. SVACC remains high until a NACK or a STOP condition is detected. |
| 5 slave | TWI_GACC AT91C_TWI_GACC | General Call ACcess (used only in Slave mode) 0: No General Call has been detected. 1: A General Call has been detected. |
| 8 slave | TWI_NACK_SLAVE AT91C_TWI_NACK_SLAVE | Not Acknowledged 0: Each data byte has been correctly received by the Master. 1: In read mode, a data byte has not been acknowledged by the Master. When NACK is set the programmer must not fill TWI_THR even if TXRDY is set, because it means that the Master will stop the data transfer or re initiate it. |
| 10 slave | TWI_SCLWS AT91C_TWI_SCLWS | Clock Wait State (used only in Slave mode) 0: The clock isnt stretched. 1: The clock is stretched. TWI_THR / TWI_RHR buffer is not filled / emptied before the emission / reception of a new character. |
| 11 slave | TWI_EOSACC AT91C_TWI_EOSACC | End Of Slave ACCess (used only in Slave mode) 0: A slave access is being performing. 1: The Slave Access is finished. |
| 12 slave | TWI_ENDRX AT91C_TWI_ENDRX | End of Receiver Transfer 0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive. 1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active. |
| 13 slave | TWI_ENDTX AT91C_TWI_ENDTX | End of Receiver Transfer 0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive. 1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active. |
| 14 slave | TWI_RXBUFF AT91C_TWI_RXBUFF | RXBUFF Interrupt 0 = PDC2 Reception Buffer is not full. 1 = PDC2 Reception Buffer is full. |
| 15 slave | TWI_TXBUFE AT91C_TWI_TXBUFE | TXBUFE Interrupt 0 = PDC2 Transmission Buffer is not empty. 1 = PDC2 Transmission Buffer is empty |
| 0 master | TWI_TXCOMP_MASTER AT91C_TWI_TXCOMP_MASTER | Transmission Completed 0: During the length of the current frame. 1: When both holding and shifter registers are empty and STOP condition has been sent or when MSEN is set (enable TWI). |
| 1 master | TWI_RXRDY AT91C_TWI_RXRDY | Receive holding register ReaDY 0: No character has been received since the last TWI_RHR read operation. 1: A byte has been received in the TWI_RHR since the last read. |
| 2 master | TWI_TXRDY_MASTER AT91C_TWI_TXRDY_MASTER | Transmit holding register ReaDY 0: The transmit holding register has not been transferred into shift register. 1: As soon as data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI). |
| 6 master | TWI_OVRE AT91C_TWI_OVRE | Overrun Error (used only in Master and Multi-master mode) 0: TWI_RHR has not been loaded while RXRDY was set. 1: TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set. |
| 8 master | TWI_NACK_MASTER AT91C_TWI_NACK_MASTER | Not Acknowledged 0: Each data byte has been correctly received by the far-end side TWI slave component. 1: A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP. |
| 12 master | TWI_ENDRX AT91C_TWI_ENDRX | End of Receiver Transfer 0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive. 1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active. |
| 13 master | TWI_ENDTX AT91C_TWI_ENDTX | End of Receiver Transfer 0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive. 1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active. |
| 14 master | TWI_RXBUFF AT91C_TWI_RXBUFF | RXBUFF Interrupt 0 = PDC2 Reception Buffer is not full. 1 = PDC2 Reception Buffer is full. |
| 15 master | TWI_TXBUFE AT91C_TWI_TXBUFE | TXBUFE Interrupt 0 = PDC2 Transmission Buffer is not empty. 1 = PDC2 Transmission Buffer is empty |
| 9 mult mast | TWI_ARBLST_MULTI_MASTER AT91C_TWI_ARBLST_MULTI_MASTER | Arbitration Lost (used only in Multimaster mode) 0: Arbitration win. 1: Arbitration lost. Another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time. |
| Offset | Name | Description |
|---|---|---|
| 0 slave | TWI_TXCOMP_SLAVE AT91C_TWI_TXCOMP_SLAVE | Transmission Completed 0: As soon as a Start is detected. 1: After a Stop or a Repeated Start + an address different from SADR is detected. |
| 1 slave | TWI_RXRDY AT91C_TWI_RXRDY | Receive holding register ReaDY 0: No character has been received since the last TWI_RHR read operation. 1: A byte has been received in the TWI_RHR since the last read. |
| 2 slave | TWI_TXRDY_SLAVE AT91C_TWI_TXRDY_SLAVE | Transmit holding register ReaDY 0: As soon as a data is written in the TWI_THR, until this data has been transmitted and acknowledged (ACK or NACK). 1: It indicates that the TWI_THR is empty and that a data has been transmitted and acknowledged. If TXRDY is high and if a NACK has been detected, it means that the transmission will be stopped. Thus when TRDY = NACK = 1, the programmer must not fill TWI_THR to avoid loosing it. |
| 3 slave | TWI_SVREAD AT91C_TWI_SVREAD | Slave READ (used only in Slave mode) When SVACC is low SVREAD is irrelevant. 0: Indicates that a write access is performed by a Master. 1: Indicates that a read access is performed by a Master. |
| 4 slave | TWI_SVACC AT91C_TWI_SVACC | Slave ACCess (used only in Slave mode) 0: TWI isnt addressed. SVACC is automatically cleared after a NACK or a STOP condition is detected. 1: Indicates that the address decoding sequence has matched. SVACC remains high until a NACK or a STOP condition is detected. |
| 5 slave | TWI_GACC AT91C_TWI_GACC | General Call ACcess (used only in Slave mode) 0: No General Call has been detected. 1: A General Call has been detected. |
| 8 slave | TWI_NACK_SLAVE AT91C_TWI_NACK_SLAVE | Not Acknowledged 0: Each data byte has been correctly received by the Master. 1: In read mode, a data byte has not been acknowledged by the Master. When NACK is set the programmer must not fill TWI_THR even if TXRDY is set, because it means that the Master will stop the data transfer or re initiate it. |
| 10 slave | TWI_SCLWS AT91C_TWI_SCLWS | Clock Wait State (used only in Slave mode) 0: The clock isnt stretched. 1: The clock is stretched. TWI_THR / TWI_RHR buffer is not filled / emptied before the emission / reception of a new character. |
| 11 slave | TWI_EOSACC AT91C_TWI_EOSACC | End Of Slave ACCess (used only in Slave mode) 0: A slave access is being performing. 1: The Slave Access is finished. |
| 12 slave | TWI_ENDRX AT91C_TWI_ENDRX | End of Receiver Transfer 0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive. 1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active. |
| 13 slave | TWI_ENDTX AT91C_TWI_ENDTX | End of Receiver Transfer 0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive. 1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active. |
| 14 slave | TWI_RXBUFF AT91C_TWI_RXBUFF | RXBUFF Interrupt 0 = PDC2 Reception Buffer is not full. 1 = PDC2 Reception Buffer is full. |
| 15 slave | TWI_TXBUFE AT91C_TWI_TXBUFE | TXBUFE Interrupt 0 = PDC2 Transmission Buffer is not empty. 1 = PDC2 Transmission Buffer is empty |
| 0 master | TWI_TXCOMP_MASTER AT91C_TWI_TXCOMP_MASTER | Transmission Completed 0: During the length of the current frame. 1: When both holding and shifter registers are empty and STOP condition has been sent or when MSEN is set (enable TWI). |
| 1 master | TWI_RXRDY AT91C_TWI_RXRDY | Receive holding register ReaDY 0: No character has been received since the last TWI_RHR read operation. 1: A byte has been received in the TWI_RHR since the last read. |
| 2 master | TWI_TXRDY_MASTER AT91C_TWI_TXRDY_MASTER | Transmit holding register ReaDY 0: The transmit holding register has not been transferred into shift register. 1: As soon as data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI). |
| 6 master | TWI_OVRE AT91C_TWI_OVRE | Overrun Error (used only in Master and Multi-master mode) 0: TWI_RHR has not been loaded while RXRDY was set. 1: TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set. |
| 8 master | TWI_NACK_MASTER AT91C_TWI_NACK_MASTER | Not Acknowledged 0: Each data byte has been correctly received by the far-end side TWI slave component. 1: A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP. |
| 12 master | TWI_ENDRX AT91C_TWI_ENDRX | End of Receiver Transfer 0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive. 1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active. |
| 13 master | TWI_ENDTX AT91C_TWI_ENDTX | End of Receiver Transfer 0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive. 1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active. |
| 14 master | TWI_RXBUFF AT91C_TWI_RXBUFF | RXBUFF Interrupt 0 = PDC2 Reception Buffer is not full. 1 = PDC2 Reception Buffer is full. |
| 15 master | TWI_TXBUFE AT91C_TWI_TXBUFE | TXBUFE Interrupt 0 = PDC2 Transmission Buffer is not empty. 1 = PDC2 Transmission Buffer is empty |
| 9 mult mast | TWI_ARBLST_MULTI_MASTER AT91C_TWI_ARBLST_MULTI_MASTER | Arbitration Lost (used only in Multimaster mode) 0: Arbitration win. 1: Arbitration lost. Another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time. |
| Offset | Name | Description |
|---|---|---|
| 0 slave | TWI_TXCOMP_SLAVE AT91C_TWI_TXCOMP_SLAVE | Transmission Completed 0: As soon as a Start is detected. 1: After a Stop or a Repeated Start + an address different from SADR is detected. |
| 1 slave | TWI_RXRDY AT91C_TWI_RXRDY | Receive holding register ReaDY 0: No character has been received since the last TWI_RHR read operation. 1: A byte has been received in the TWI_RHR since the last read. |
| 2 slave | TWI_TXRDY_SLAVE AT91C_TWI_TXRDY_SLAVE | Transmit holding register ReaDY 0: As soon as a data is written in the TWI_THR, until this data has been transmitted and acknowledged (ACK or NACK). 1: It indicates that the TWI_THR is empty and that a data has been transmitted and acknowledged. If TXRDY is high and if a NACK has been detected, it means that the transmission will be stopped. Thus when TRDY = NACK = 1, the programmer must not fill TWI_THR to avoid loosing it. |
| 3 slave | TWI_SVREAD AT91C_TWI_SVREAD | Slave READ (used only in Slave mode) When SVACC is low SVREAD is irrelevant. 0: Indicates that a write access is performed by a Master. 1: Indicates that a read access is performed by a Master. |
| 4 slave | TWI_SVACC AT91C_TWI_SVACC | Slave ACCess (used only in Slave mode) 0: TWI isnt addressed. SVACC is automatically cleared after a NACK or a STOP condition is detected. 1: Indicates that the address decoding sequence has matched. SVACC remains high until a NACK or a STOP condition is detected. |
| 5 slave | TWI_GACC AT91C_TWI_GACC | General Call ACcess (used only in Slave mode) 0: No General Call has been detected. 1: A General Call has been detected. |
| 8 slave | TWI_NACK_SLAVE AT91C_TWI_NACK_SLAVE | Not Acknowledged 0: Each data byte has been correctly received by the Master. 1: In read mode, a data byte has not been acknowledged by the Master. When NACK is set the programmer must not fill TWI_THR even if TXRDY is set, because it means that the Master will stop the data transfer or re initiate it. |
| 10 slave | TWI_SCLWS AT91C_TWI_SCLWS | Clock Wait State (used only in Slave mode) 0: The clock isnt stretched. 1: The clock is stretched. TWI_THR / TWI_RHR buffer is not filled / emptied before the emission / reception of a new character. |
| 11 slave | TWI_EOSACC AT91C_TWI_EOSACC | End Of Slave ACCess (used only in Slave mode) 0: A slave access is being performing. 1: The Slave Access is finished. |
| 12 slave | TWI_ENDRX AT91C_TWI_ENDRX | End of Receiver Transfer 0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive. 1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active. |
| 13 slave | TWI_ENDTX AT91C_TWI_ENDTX | End of Receiver Transfer 0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive. 1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active. |
| 14 slave | TWI_RXBUFF AT91C_TWI_RXBUFF | RXBUFF Interrupt 0 = PDC2 Reception Buffer is not full. 1 = PDC2 Reception Buffer is full. |
| 15 slave | TWI_TXBUFE AT91C_TWI_TXBUFE | TXBUFE Interrupt 0 = PDC2 Transmission Buffer is not empty. 1 = PDC2 Transmission Buffer is empty |
| 0 master | TWI_TXCOMP_MASTER AT91C_TWI_TXCOMP_MASTER | Transmission Completed 0: During the length of the current frame. 1: When both holding and shifter registers are empty and STOP condition has been sent or when MSEN is set (enable TWI). |
| 1 master | TWI_RXRDY AT91C_TWI_RXRDY | Receive holding register ReaDY 0: No character has been received since the last TWI_RHR read operation. 1: A byte has been received in the TWI_RHR since the last read. |
| 2 master | TWI_TXRDY_MASTER AT91C_TWI_TXRDY_MASTER | Transmit holding register ReaDY 0: The transmit holding register has not been transferred into shift register. 1: As soon as data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI). |
| 6 master | TWI_OVRE AT91C_TWI_OVRE | Overrun Error (used only in Master and Multi-master mode) 0: TWI_RHR has not been loaded while RXRDY was set. 1: TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set. |
| 8 master | TWI_NACK_MASTER AT91C_TWI_NACK_MASTER | Not Acknowledged 0: Each data byte has been correctly received by the far-end side TWI slave component. 1: A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP. |
| 12 master | TWI_ENDRX AT91C_TWI_ENDRX | End of Receiver Transfer 0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive. 1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active. |
| 13 master | TWI_ENDTX AT91C_TWI_ENDTX | End of Receiver Transfer 0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive. 1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active. |
| 14 master | TWI_RXBUFF AT91C_TWI_RXBUFF | RXBUFF Interrupt 0 = PDC2 Reception Buffer is not full. 1 = PDC2 Reception Buffer is full. |
| 15 master | TWI_TXBUFE AT91C_TWI_TXBUFE | TXBUFE Interrupt 0 = PDC2 Transmission Buffer is not empty. 1 = PDC2 Transmission Buffer is empty |
| 9 mult mast | TWI_ARBLST_MULTI_MASTER AT91C_TWI_ARBLST_MULTI_MASTER | Arbitration Lost (used only in Multimaster mode) 0: Arbitration win. 1: Arbitration lost. Another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time. |
| Offset | Name | Description |
|---|---|---|
| 0 slave | TWI_TXCOMP_SLAVE AT91C_TWI_TXCOMP_SLAVE | Transmission Completed 0: As soon as a Start is detected. 1: After a Stop or a Repeated Start + an address different from SADR is detected. |
| 1 slave | TWI_RXRDY AT91C_TWI_RXRDY | Receive holding register ReaDY 0: No character has been received since the last TWI_RHR read operation. 1: A byte has been received in the TWI_RHR since the last read. |
| 2 slave | TWI_TXRDY_SLAVE AT91C_TWI_TXRDY_SLAVE | Transmit holding register ReaDY 0: As soon as a data is written in the TWI_THR, until this data has been transmitted and acknowledged (ACK or NACK). 1: It indicates that the TWI_THR is empty and that a data has been transmitted and acknowledged. If TXRDY is high and if a NACK has been detected, it means that the transmission will be stopped. Thus when TRDY = NACK = 1, the programmer must not fill TWI_THR to avoid loosing it. |
| 3 slave | TWI_SVREAD AT91C_TWI_SVREAD | Slave READ (used only in Slave mode) When SVACC is low SVREAD is irrelevant. 0: Indicates that a write access is performed by a Master. 1: Indicates that a read access is performed by a Master. |
| 4 slave | TWI_SVACC AT91C_TWI_SVACC | Slave ACCess (used only in Slave mode) 0: TWI isnt addressed. SVACC is automatically cleared after a NACK or a STOP condition is detected. 1: Indicates that the address decoding sequence has matched. SVACC remains high until a NACK or a STOP condition is detected. |
| 5 slave | TWI_GACC AT91C_TWI_GACC | General Call ACcess (used only in Slave mode) 0: No General Call has been detected. 1: A General Call has been detected. |
| 8 slave | TWI_NACK_SLAVE AT91C_TWI_NACK_SLAVE | Not Acknowledged 0: Each data byte has been correctly received by the Master. 1: In read mode, a data byte has not been acknowledged by the Master. When NACK is set the programmer must not fill TWI_THR even if TXRDY is set, because it means that the Master will stop the data transfer or re initiate it. |
| 10 slave | TWI_SCLWS AT91C_TWI_SCLWS | Clock Wait State (used only in Slave mode) 0: The clock isnt stretched. 1: The clock is stretched. TWI_THR / TWI_RHR buffer is not filled / emptied before the emission / reception of a new character. |
| 11 slave | TWI_EOSACC AT91C_TWI_EOSACC | End Of Slave ACCess (used only in Slave mode) 0: A slave access is being performing. 1: The Slave Access is finished. |
| 12 slave | TWI_ENDRX AT91C_TWI_ENDRX | End of Receiver Transfer 0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive. 1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active. |
| 13 slave | TWI_ENDTX AT91C_TWI_ENDTX | End of Receiver Transfer 0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive. 1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active. |
| 14 slave | TWI_RXBUFF AT91C_TWI_RXBUFF | RXBUFF Interrupt 0 = PDC2 Reception Buffer is not full. 1 = PDC2 Reception Buffer is full. |
| 15 slave | TWI_TXBUFE AT91C_TWI_TXBUFE | TXBUFE Interrupt 0 = PDC2 Transmission Buffer is not empty. 1 = PDC2 Transmission Buffer is empty |
| 0 master | TWI_TXCOMP_MASTER AT91C_TWI_TXCOMP_MASTER | Transmission Completed 0: During the length of the current frame. 1: When both holding and shifter registers are empty and STOP condition has been sent or when MSEN is set (enable TWI). |
| 1 master | TWI_RXRDY AT91C_TWI_RXRDY | Receive holding register ReaDY 0: No character has been received since the last TWI_RHR read operation. 1: A byte has been received in the TWI_RHR since the last read. |
| 2 master | TWI_TXRDY_MASTER AT91C_TWI_TXRDY_MASTER | Transmit holding register ReaDY 0: The transmit holding register has not been transferred into shift register. 1: As soon as data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI). |
| 6 master | TWI_OVRE AT91C_TWI_OVRE | Overrun Error (used only in Master and Multi-master mode) 0: TWI_RHR has not been loaded while RXRDY was set. 1: TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set. |
| 8 master | TWI_NACK_MASTER AT91C_TWI_NACK_MASTER | Not Acknowledged 0: Each data byte has been correctly received by the far-end side TWI slave component. 1: A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP. |
| 12 master | TWI_ENDRX AT91C_TWI_ENDRX | End of Receiver Transfer 0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is inactive. 1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the receiver is active. |
| 13 master | TWI_ENDTX AT91C_TWI_ENDTX | End of Receiver Transfer 0 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is inactive. 1 = The End of Transfer signal from the Peripheral Data Controller channel dedicated to the transmitter is active. |
| 14 master | TWI_RXBUFF AT91C_TWI_RXBUFF | RXBUFF Interrupt 0 = PDC2 Reception Buffer is not full. 1 = PDC2 Reception Buffer is full. |
| 15 master | TWI_TXBUFE AT91C_TWI_TXBUFE | TXBUFE Interrupt 0 = PDC2 Transmission Buffer is not empty. 1 = PDC2 Transmission Buffer is empty |
| 9 mult mast | TWI_ARBLST_MULTI_MASTER AT91C_TWI_ARBLST_MULTI_MASTER | Arbitration Lost (used only in Multimaster mode) 0: Arbitration win. 1: Arbitration lost. Another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time. |