SDRAM Controller Interface Peripheral

SDRC (AT91S_SDRC) 0xFFFFFFB0 (AT91C_BASE_SDRC)

SDRC Software API (AT91S_SDRC)

OffsetFieldDescription
0x0SDRC_MRSDRAM Controller Mode Register
0x4SDRC_TRSDRAM Controller Refresh Timer Register
0x8SDRC_CRSDRAM Controller Configuration Register
0xCSDRC_SRRSDRAM Controller Self Refresh Register
0x10SDRC_LPRSDRAM Controller Low Power Register
0x14SDRC_IERSDRAM Controller Interrupt Enable Register
0x18SDRC_IDRSDRAM Controller Interrupt Disable Register
0x1CSDRC_IMRSDRAM Controller Interrupt Mask Register
0x20SDRC_ISRSDRAM Controller Interrupt Mask Register
0x24SDRC_VER (IPB_VER)SDRAM Controller Version Register

SDRC Register Description

SDRC: AT91_REG SDRC_MR SDRAM Controller Mode Register

OffsetNameDescription
3..0SDRC_MODE
AT91C_SDRC_MODE
Mode
0: Normal Mode.
1: Issue a NOP Command at every access.
2: Issue a All Banks Precharge Command at every access.

3: Issue a Load Mode Register at every access.
4: Issue a Refresh
ValueLabelDescription
0SDRC_MODE_NORMAL_CMD
AT91C_SDRC_MODE_NORMAL_CMD

Normal Mode
1SDRC_MODE_NOP_CMD
AT91C_SDRC_MODE_NOP_CMD

NOP Command
2SDRC_MODE_PRCGALL_CMD
AT91C_SDRC_MODE_PRCGALL_CMD

All Banks Precharge Command
3SDRC_MODE_LMR_CMD
AT91C_SDRC_MODE_LMR_CMD

Load Mode Register Command
4SDRC_MODE_RFSH_CMD
AT91C_SDRC_MODE_RFSH_CMD

Refresh Command
4SDRC_DBW
AT91C_SDRC_DBW
Data Bus Width
0: 32 bits.
1: 16bits.
ValueLabelDescription
0SDRC_DBW_32_BITS
AT91C_SDRC_DBW_32_BITS

32 Bits datas bus
1SDRC_DBW_16_BITS
AT91C_SDRC_DBW_16_BITS

16 Bits datas bus

SDRC: AT91_REG SDRC_TR SDRAM Controller Refresh Timer Register

OffsetNameDescription
11..0SDRC_COUNT
AT91C_SDRC_COUNT
Refresh Counter

SDRC: AT91_REG SDRC_CR SDRAM Controller Configuration Register

OffsetNameDescription
1..0SDRC_NC
AT91C_SDRC_NC
Number of Column Bits
0: 8.
1: 9.
3: 10.
3: 11.
ValueLabelDescription
0SDRC_NC_8
AT91C_SDRC_NC_8

8 Bits
1SDRC_NC_9
AT91C_SDRC_NC_9

9 Bits
2SDRC_NC_10
AT91C_SDRC_NC_10

10 Bits
3SDRC_NC_11
AT91C_SDRC_NC_11

11 Bits
3..2SDRC_NR
AT91C_SDRC_NR
Number of Row Bits
0: 11.
1: 12.
3: 13.
3: Reserved.
ValueLabelDescription
0SDRC_NR_11
AT91C_SDRC_NR_11

11 Bits
1SDRC_NR_12
AT91C_SDRC_NR_12

12 Bits
2SDRC_NR_13
AT91C_SDRC_NR_13

13 Bits
4SDRC_NB
AT91C_SDRC_NB
Number of Banks
0: 2.
1: 4.
ValueLabelDescription
0SDRC_NB_2_BANKS
AT91C_SDRC_NB_2_BANKS

2 banks
1SDRC_NB_4_BANKS
AT91C_SDRC_NB_4_BANKS

4 banks
6..5SDRC_CAS
AT91C_SDRC_CAS
CAS Latency
0: Reserved.
1: Reserved.
2: 2.
3: Reserved.
ValueLabelDescription
2SDRC_CAS_2
AT91C_SDRC_CAS_2

2 cycles
10..7SDRC_TWR
AT91C_SDRC_TWR
Number of Write Recovery Time Cycles
14..11SDRC_TRC
AT91C_SDRC_TRC
Number of RAS Cycle Time Cycles
18..15SDRC_TRP
AT91C_SDRC_TRP
Number of RAS Precharge Time Cycles
22..19SDRC_TRCD
AT91C_SDRC_TRCD
Number of RAS to CAS Delay Cycles
26..23SDRC_TRAS
AT91C_SDRC_TRAS
Number of RAS Active Time Cycles
30..27SDRC_TXSR
AT91C_SDRC_TXSR
Number of Command Recovery Time Cycles

SDRC: AT91_REG SDRC_SRR SDRAM Controller Self Refresh Register

OffsetNameDescription
0SDRC_SRCB
AT91C_SDRC_SRCB
Self-refresh Command Bit

SDRC: AT91_REG SDRC_LPR SDRAM Controller Low Power Register

OffsetNameDescription
0SDRC_LPCB
AT91C_SDRC_LPCB
Low-power Command Bit

SDRC: AT91_REG SDRC_IER SDRAM Controller Interrupt Enable Register

OffsetNameDescription
0SDRC_RES
AT91C_SDRC_RES
Refresh Error Status

SDRC: AT91_REG SDRC_IDR SDRAM Controller Interrupt Disable Register

OffsetNameDescription
0SDRC_RES
AT91C_SDRC_RES
Refresh Error Status

SDRC: AT91_REG SDRC_IMR SDRAM Controller Interrupt Mask Register

OffsetNameDescription
0SDRC_RES
AT91C_SDRC_RES
Refresh Error Status

SDRC: AT91_REG SDRC_ISR SDRAM Controller Interrupt Mask Register

OffsetNameDescription
0SDRC_RES
AT91C_SDRC_RES
Refresh Error Status

SDRC: AT91_REG IPB_VER SDRAM Controller Version Register

OffsetNameDescription
11..0SDRC_VERSION
AT91C_SDRC_VERSION
IP version of the macrocell
3..1SDRC_MFN
AT91C_SDRC_MFN