#include <avr/io.h>
#include <util/delay.h>
#include <stdint.h>
#include <avr/interrupt.h>

//define LEER PA0
//define LEER PA1
//define RESET PA2

#define LED6 PB0
#define LED7 PB1
#define LED8 PB2
#define IN3 PB3 //PCINT3
#define IN2 PB4 //PCINT4
#define SDA PB5
#define IN1 PB6 //PCINT6
#define SCL PB7

#define LED1 PD0
#define LED2 PD1
#define LED3 PD2
#define LED4 PD3
#define LED5 PD4
#define T1 PD5
//define LEER PD6

/* SLAVE-ADRESS */
#define slave_address 0b00001000 //Adresse 0x08 ohne R/W Bit
//Master write -> TWDR = 0b00010000
//Master read -> TWDR = 0b00010001

/****************************************************************************
Variabeln STATUS
****************************************************************************/

volatile unsigned char STATUS0 = 0;
volatile unsigned char STATUS1 = 0;

/****************************************************************************
Variabeln TWI
****************************************************************************/

volatile unsigned char STATUS_TWI = 0;
volatile unsigned char DATA[7];
volatile unsigned char i_TWI; //TWI Zähler für Array-Byte

/****************************************************************************
Hauptprogramm
****************************************************************************/

int main(void)
{
	//Port settings
	DDRB |= (1<<LED6) | (1<<LED7) | (1<<LED8);
	DDRD |= (1<<LED1) | (1<<LED2) | (1<<LED3) | (1<<LED4) | (1<<LED5);
	PORTB |= (1<<IN1) | (1<<IN2) | (1<<IN3); //Pullup für PCINT
	
	//TWI settings
	USICR |= (1<<USISIE) | (1<<USIWM1) | (1<<USICS1) | (1<<USICS0); //Start Condition Interrupt Enable, TWI: Use SDA and SCL, external Clock Source on negative edge
	PORTB |= (1<<SCL);
	DDRB |= (1<<SCL); //TWI has control over SCL line
	USISR |= ((USISIF) | (1<<USIOIF)); //clear Start Interrupt- and Counter Overflow Flag
	/* !!! SLAVE ADRESSE siehe Definition slave_address !!! */

	
	sei();
	
	
	while (1)
	{
		/* TWI STOP received */
		if (USISR & (1<<USIPF))
		{
			USICR &= ~((1<<USIOIE) | (1<<USIWM0));
			USISR |= (1<<USIPF);
			DDRB &= ~((1<<SDA) | (1<<SCL));
			STATUS1 &= ~(1<<0);
			STATUS_TWI = 0;
		}
		
		/* TWI new Data */
		if (STATUS0 & (1<<0))
		{
			PORTB &= ~((1<<LED8) | (1<<LED7) | (1<<LED6));
			PORTD &= ~((1<<LED5) | (1<<LED4) | (1<<LED3) | (1<<LED2) | (1<<LED1));
			PORTB |= ((DATA[0] & 0b11100000) >> 5); //LED 6-8
			PORTD |= (DATA[0] & 0b00011111); //LED 1-5
			STATUS0 &= ~(1<<0);
		}
	}
}

/****************************************************************************
Interrupt TWI START
****************************************************************************/

ISR(USI_START_vect)
{
	STATUS_TWI = 0b00000001; //START empfangen
	while (PINB & (1<<SCL)); //warten bis SCL auf low gesetzt wurde
	USISR = 0xF0; //clear all Flags, clear counter
	USICR |= (1<<USIOIE) | (1<<USIWM0); //TWI Overflow interrupt enable
	i_TWI = 1;
	STATUS1 |= (1<<0);
}

/****************************************************************************
Interrupt TWI OVF
****************************************************************************/

ISR(USI_OVERFLOW_vect)
{
	unsigned char tmpDATA = USIDR;
	
	/* ACK TX */
	if (STATUS_TWI & (1<<6))
	{
		if (tmpDATA & (1<<0)) {STATUS_TWI = 0;} //TWI beendet
		else
		{
			USIDR = DATA[i_TWI];
			//PORTB |= (1<<SDA);
			DDRB |= (1<<SDA);
		}
		STATUS_TWI &= ~(1<<6);
	}
	
	/* ACK RX */
	else if (STATUS_TWI & (1<<7))
	{
		if (STATUS_TWI == 0b10001000) {USIDR = DATA[i_TWI]; /*PORTB |= (1<<SDA);*/} //für TX-Mode Daten laden
		else {DDRB &= ~(1<<SDA);}
		if (STATUS_TWI == 0b10000011) {DDRB &= ~(1<<SDA); STATUS_TWI = 0;} //TWI beendet
		STATUS_TWI &= ~(1<<7);
	}

	/* Slave Adresse emfangen */
	else if (STATUS_TWI == 0b00000001)
	{
		if (((tmpDATA & 0b11111110) >> 1) != slave_address) //Falsche Slave-Adresse, TWI Beenden
		{
			STATUS_TWI = 0;
			USICR &= ~((1<<USIOIE) | (1<<USIWM0));
		}
		else //richtige Slave-Adresse
		{
			DDRB |= (1<<SDA);
			USISR = 0b00001110; //counter für ACK
			if (tmpDATA & (1<<0)) {STATUS_TWI = 0b10001000;} //Slave TX, ACK abwarten
			else {STATUS_TWI = 0b10000010;} //Slave RX, ACK abwarten
		}
	}

	/* RX-Mode Byte 1 */
	else if (STATUS_TWI == 0b00000010)
	{
		DDRB |= (1<<SDA);
		USISR = 0b00001110; //counter für ACK
		DATA[0] = tmpDATA;
		STATUS_TWI = 0b10000011; //ACK abwarten
		STATUS0 |= (1<<0); //TWI new data
	}

	/* TX-Mode Byte 1-6 */
	else if (STATUS_TWI & (1<<3))
	{
		DDRB &= ~(1<<SDA);
		PORTB &= ~(1<<SDA);
		USISR = 0b00001110; //counter für ACK
		STATUS_TWI ++;
		STATUS_TWI |= (1<<6); //ACK abwarten
		i_TWI ++;
	}

	USISR |= (1<<USIOIF); //clear Overflow Flag
}