;---------------------------------------------- ; Register Declarations for the at89s8252 Processor ; auf Basis des 8051, geändert von Bub, noch nicht vollständig ;---------------------------------------------- ; BYTE Register P0 DATA 80H P1 DATA 90H P2 DATA 0A0H P3 DATA 0B0H PSW DATA 0D0H ACC DATA 0E0H B DATA 0F0H SP DATA 81H DPL DATA 82H DPH DATA 83H DP0L DATA 82H ;Data-Pointer0 Lowbyte DP0H DATA 83H ;Data-Pointer0 Highbyte DP1L DATA 84H ;Data-Pointer1 Lowbyte DP1H DATA 85H ;Data-Pointer1 Highbyte SPDR DATA 86H ;SPI Control register PCON DATA 87H TCON DATA 88H TMOD DATA 89H TL0 DATA 8AH TL1 DATA 8BH TH0 DATA 8CH TH1 DATA 8DH IE DATA 0A8H IP DATA 0B8H SCON DATA 98H SBUF DATA 99H WMCON DATA 96H ;Watchdog and Memory Control reg SPSR DATA 0AAH ;SPI status register T2CON DATA 0C8H ;Timer 2 Kontrollregister T2MOD DATA 0C9H ;Timer 2 Modusregister RCAP2L DATA 0CAH ;Reload Capture Timer2 reg. low byte RCAP2H DATA 0CBH ;Reload Capture Timer2 reg. high byte TL2 DATA 0CCH ;Timer 2 Lowbyte TH2 DATA 0CDH ;Timer 2 Highbyte SPCR DATA 0D5H ;SPI control register ; BIT Register ; PSW CY BIT 0D7H AC BIT 0D6H F0 BIT 0D5H RS1 BIT 0D4H RS0 BIT 0D3H OV BIT 0D2H P BIT 0D0H ; TCON TF1 BIT 8FH TR1 BIT 8EH TF0 BIT 8DH TR0 BIT 8CH IE1 BIT 8BH IT1 BIT 8AH IE0 BIT 89H IT0 BIT 88H ; IE EA BIT 0AFH EAL BIT 0AFH ;Name bei anderen 8051ern ET2 BIT 0ADH ;Enable Timer2-Interrupt ES BIT 0ACH ET1 BIT 0ABH EX1 BIT 0AAH ET0 BIT 0A9H EX0 BIT 0A8H ; IP PS BIT 0BCH PT1 BIT 0BBH PX1 BIT 0BAH PT0 BIT 0B9H PX0 BIT 0B8H ; P3 RD BIT 0B7H WR BIT 0B6H T1 BIT 0B5H T0 BIT 0B4H INT1 BIT 0B3H INT0 BIT 0B2H TXD BIT 0B1H RXD BIT 0B0H ; SCON SM0 BIT 9FH SM1 BIT 9EH SM2 BIT 9DH REN BIT 9CH TB8 BIT 9BH RB8 BIT 9AH TI BIT 99H RI BIT 98H ; T2CON CPRL2 BIT 0C8H ;Capture Reload select CT2 BIT 0C9H ;Timer or Counter Select TR2 BIT 0CAH ;Timer2 run EXEN2 BIT 0CBH ;Timer2 External Enable TCLK BIT 0CCH ;Transmit Clock Enable RCLK BIT 0CDH ;Receive Clock Enable EXF2 BIT 0CEH ;Timer2 External Flag TF2 BIT 0CFH ;Timer 2 Overflow Flag