void SSD1963_Init(){ //SOFTWARE RESET SSD1963_Write_cmd(0x01); delay_ms(5); //Wait a stable condition //SOFTWARE RESET SSD1963_Write_cmd(0x01); delay_ms(5); //Wait a stable condition //SOFTWARE RESET SSD1963_Write_cmd(0x01); delay_ms(5); //Wait a stable condition //SET THE INTERNAL PLL NM SSD1963_Write_cmd(0xE2); SSD1963_Write_data(0x0023); //Set Multiplier to 35 SSD1963_Write_data(0x0002); //Set Divider to 2 SSD1963_Write_data(0x0054); //Set 10Mhz*35/2=175Mhz PLL clock //ENABLE PLL SSD1963_Write_cmd(0xE0); SSD1963_Write_data(0x0001); //Reference clock , Enable PLL delay_us(10); //Wait a stable condition SSD1963_Write_cmd(0xE0); SSD1963_Write_data(0x0003); //PLL clock , Enable PLL delay_us(10); //Wait a stable condition //SOFTWARE RESET SSD1963_Write_cmd(0x01); delay_ms(20); //Wait a stable condition //PIXEL CLOCK SETTING (LSHIFT Frequency) SSD1963_Write_cmd(0xE6); SSD1963_Write_data(0x0003); //Highest 4bits SSD1963_Write_data(0x0033); //Mid 8bits SSD1963_Write_data(0x0033); //Low 8bits, 175MhzPLL*(209715 PCLK +1)/2^20=875Hz //LCD MODE AND SPECIFICATIONS SSD1963_Write_cmd(0xB0); SSD1963_Write_data(0x0020); //24bit TFT panel, Rising Edge, Active Low SSD1963_Write_data(0x0000); //HSYNC+VSYNC+DE mode TFT panel SSD1963_Write_data((799>>8)&0x0007); //Highest 3bits HPS SSD1963_Write_data(799 & 0x00FF); //Lowest 8bist HPS, Horizontal Panel Size 800px SSD1963_Write_data((479>>8)&0x0007); //Highest 3bits VPS SSD1963_Write_data(479 & 0x00FF); //Lowest 8bist VPS, Vertical Panel Size 480px SSD1963_Write_data(0x0000); //RGB sequence for even and odd lines //Horizontal Period HSYNC Settings SSD1963_Write_cmd(0xB4); SSD1963_Write_data(0x0004); //Highest 3bits HT SSD1963_Write_data(0x001F); //Lowest 8bist HT, Horizontal Total Period 1055PCK+1 SSD1963_Write_data(0x0000); //Highest 3bits HPS SSD1963_Write_data(0x00D2); //Lowest 8bist HPS, Horizontal non display Period 210PCK+1 SSD1963_Write_data(0x0000); //HPW, Horizontal Pulse Width 0PCK+1 SSD1963_Write_data(0x0000); //Highest 3bits LPS SSD1963_Write_data(0x0000); //Lowest 8bist LPS, Horizontal sync pulse Period 0PCK+1 SSD1963_Write_data(0x0000); //LPSPP, Horizontal sync pulse start position 0PCK //Horizontal Period HSYNC Settings SSD1963_Write_cmd(0xB6); SSD1963_Write_data(0x0002); //Highest 3bits VT SSD1963_Write_data(0x000C); //Lowest 8bist VT, Vertical Total Period 524PCK+1 SSD1963_Write_data(0x0000); //Highest 3bits VPS SSD1963_Write_data(0x0022); //Lowest 8bist VPS, Vertical non display Period 34PCK+1 SSD1963_Write_data(0x0000); //VPW, Vertical Pulse Width 0PCK+1 SSD1963_Write_data(0x0000); //Highest 3bits VPS SSD1963_Write_data(0x0000); //Lowest 8bist VPS, Vertical sync pulse Period 0PCK+1 //SSD1963 GPIO CONFIGURATION SSD1963_Write_cmd(0xB8); SSD1963_Write_data(0x000F); //GPIO of the SSD1963 are output controlled by host SSD1963_Write_data(0x0001); //GPIO0 operates normally //SET GPIO VALUES SSD1963_Write_cmd(0xBA); SSD1963_Write_data(0x0001); //GPIO0=1 -> LCD ON //write_data_565(0x0000); //GPIO0=0 -> LCD OFF //SET ADRESSING MODE SSD1963_Write_cmd(0x36); SSD1963_Write_data(0x0008); //FrameBuffer RGB -> DisplayPanel BGR //SET PIXEL FORMAT SSD1963_Write_cmd(0x3A); SSD1963_Write_data(0x0050); //16bit per pixel //SET PIXEL DATA INTERFACE SSD1963_Write_cmd(0xF0); SSD1963_Write_data(0x0003); //16bit at 565 color interface //SET IMAGE POST PROCESSOR SSD1963_Write_cmd(0xBC); SSD1963_Write_data(0x0040); //Default Contrast Value SSD1963_Write_data(0x0080); //Default Brightness Value SSD1963_Write_data(0x0040); //Default Saturation Value SSD1963_Write_data(0x0001); //Post Processor is Enabled delay_us(5); //DISPLAY THE FRAME BUFFER ON THE DEVICE SSD1963_Write_cmd(0x29); //BLANKS THE DEVICE WITH UNCHANGED BUFFER //write_command_565(0x28); //SET PWM TO THE BACKLIGHT DRIVER SSD1963_Write_cmd(0xBE); SSD1963_Write_data(0x0006); //PWMF = 175MHz/(256*6)/256 = SSD1963_Write_data(0x0080); //PWM duty cycle = 50% SSD1963_Write_data(0x0000); //PWM is controlled by host and ENABLED SSD1963_Write_data(0x00F0); //DBC Manual Brightness 98% SSD1963_Write_data(0x0000); //DBC Minimum Brightness 10% SSD1963_Write_data(0x0000); //Brightness Prescaler to the dimmest //DBC CONFIGURATION (Dynamic Brightness Control) SSD1963_Write_cmd(0x00D0); SSD1963_Write_data(0x0000); //DBC is ENABLED } uint8_t FMC_SSD1963_FAST_Init(void){ FMC_NORSRAMInitTypeDef FMC_NORSRAMInitDef; FMC_NORSRAMTimingInitTypeDef FMC_NORSRAMTimingInitDef_Write, FMC_NORSRAMTimingInitDef_Read; /* Enable FMC clock */ RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE); /* FMC SSD1963 as a NORSRAM device initialization sequence ---*/ /* Step 1 ----------------------------------------------------------*/ /* Timing configuration for 84 Mhz of SD clock frequency (168Mhz/2) */ FMC_NORSRAMTimingInitDef_Write.FMC_AddressSetupTime = 0x01; FMC_NORSRAMTimingInitDef_Write.FMC_AddressHoldTime = 0x00; FMC_NORSRAMTimingInitDef_Write.FMC_DataSetupTime = 0x01; FMC_NORSRAMTimingInitDef_Write.FMC_BusTurnAroundDuration = 0x00; FMC_NORSRAMTimingInitDef_Write.FMC_CLKDivision = 0x01; FMC_NORSRAMTimingInitDef_Write.FMC_DataLatency = 0x00; FMC_NORSRAMTimingInitDef_Write.FMC_AccessMode = FMC_AccessMode_A; /* Timing configuration for 84 Mhz of SD clock frequency (168Mhz/2) */ FMC_NORSRAMTimingInitDef_Read.FMC_AddressSetupTime = 0x0A; FMC_NORSRAMTimingInitDef_Read.FMC_AddressHoldTime = 0x00; FMC_NORSRAMTimingInitDef_Read.FMC_DataSetupTime = 0x0A; FMC_NORSRAMTimingInitDef_Read.FMC_BusTurnAroundDuration = 0x00; FMC_NORSRAMTimingInitDef_Read.FMC_CLKDivision = 0x01; FMC_NORSRAMTimingInitDef_Read.FMC_DataLatency = 0x00; FMC_NORSRAMTimingInitDef_Read.FMC_AccessMode = FMC_AccessMode_A; /* FMC SDRAM control configuration */ FMC_NORSRAMInitDef.FMC_Bank = FMC_Bank1_NORSRAM1; FMC_NORSRAMInitDef.FMC_DataAddressMux = FMC_DataAddressMux_Disable; FMC_NORSRAMInitDef.FMC_MemoryType = FMC_MemoryType_SRAM; FMC_NORSRAMInitDef.FMC_MemoryDataWidth = FMC_NORSRAM_MemoryDataWidth_16b; FMC_NORSRAMInitDef.FMC_BurstAccessMode = FMC_BurstAccessMode_Disable; FMC_NORSRAMInitDef.FMC_AsynchronousWait = FMC_AsynchronousWait_Disable; FMC_NORSRAMInitDef.FMC_WaitSignalPolarity = FMC_WaitSignalPolarity_Low; FMC_NORSRAMInitDef.FMC_WrapMode = FMC_WrapMode_Disable; FMC_NORSRAMInitDef.FMC_WaitSignalActive = FMC_WaitSignalActive_BeforeWaitState; FMC_NORSRAMInitDef.FMC_WriteOperation = FMC_WriteOperation_Enable; FMC_NORSRAMInitDef.FMC_WaitSignal = FMC_WaitSignal_Disable; FMC_NORSRAMInitDef.FMC_ExtendedMode = FMC_ExtendedMode_Disable; FMC_NORSRAMInitDef.FMC_WriteBurst = FMC_WriteBurst_Disable; FMC_NORSRAMInitDef.FMC_ContinousClock = FMC_CClock_SyncOnly; //FMC_CClock_SyncAsync FMC_NORSRAMInitDef.FMC_ReadWriteTimingStruct = &FMC_NORSRAMTimingInitDef_Read; FMC_NORSRAMInitDef.FMC_WriteTimingStruct = &FMC_NORSRAMTimingInitDef_Write; /* DISABLING THE NORSRAM BANK WHILE CHANGING SPEED */ FMC_NORSRAMCmd(FMC_Bank1_NORSRAM1, DISABLE); /* FMC NORSRAM bank initialization */ FMC_NORSRAMInit(&FMC_NORSRAMInitDef); /* FMC NORSRAM bank enable */ FMC_NORSRAMCmd(FMC_Bank1_NORSRAM1, ENABLE); return 1; }