Static Timing Analysis

Project : UDBFIFO_Example01
Build Time : 07/05/16 20:55:43
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
Note: If your design will only ever run at typical room temperatures, selecting the narrower temperature range in the system DWR for your application helps the tool to find timing-compliant routing solutions.
Violation Source Clock Destination Clock Slack(ns)
Async
Clock(routed) Clock
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
Clock(routed) Clock(routed) 2.000 MHz 2.000 MHz N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 57.395 MHz
Clock CyMASTER_CLK 2.000 MHz 2.000 MHz N/A
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\TopDesign_1:Datapath_1:u0\/f0_bus_stat_comb DMA_TX/dmareq 57.395 MHz 17.423 24.244
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,4) 1 \TopDesign_1:Datapath_1:u0\ \TopDesign_1:Datapath_1:u0\/busclk \TopDesign_1:Datapath_1:u0\/f0_bus_stat_comb 3.110
Route 1 Net_172 \TopDesign_1:Datapath_1:u0\/f0_bus_stat_comb DMA_TX/dmareq 7.213
drqcell1 [DrqContainer=(0)][DrqId=(0)] 1 DMA_TX SETUP 7.100
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\TopDesign_1:Datapath_1:u0\/f0_bus_stat_comb DMA_TX/dmareq 10.323
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,4) 1 \TopDesign_1:Datapath_1:u0\ \TopDesign_1:Datapath_1:u0\/busclk \TopDesign_1:Datapath_1:u0\/f0_bus_stat_comb 3.110
Route 1 Net_172 \TopDesign_1:Datapath_1:u0\/f0_bus_stat_comb DMA_TX/dmareq 7.213
drqcell1 [DrqContainer=(0)][DrqId=(0)] 1 DMA_TX HOLD 0.000
Clock Skew 0.000
+ Asynchronous Clock Crossing Section
+ Source Clock Clock(routed)
Source Destination Delay (ns)
ClockBlock/dclk_0 \TopDesign_1:Datapath_1:u0\/d0_load 9.397
Type Location Fanout Instance/Net Source Dest Delay (ns)
clockblockcell F(Clock,0) 1 ClockBlock Input Delay ClockBlock/dclk_0 0.000
Route 1 Net_11_local ClockBlock/dclk_0 \TopDesign_1:Datapath_1:u0\/d0_load 7.077
datapathcell1 U(3,4) 1 \TopDesign_1:Datapath_1:u0\ SETUP 2.320
Clock Skew 0.000
+ Clock To Output Section
+ Clock
Source Destination Delay (ns)
\TopDesign_1:Datapath_1:u0\/z0_comb tc(0)_PAD 22.782
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,4) 1 \TopDesign_1:Datapath_1:u0\ \TopDesign_1:Datapath_1:u0\/clock \TopDesign_1:Datapath_1:u0\/z0_comb 2.290
Route 1 Net_30 \TopDesign_1:Datapath_1:u0\/z0_comb tc(0)/pin_input 5.612
iocell3 P0[4] 1 tc(0) tc(0)/pin_input tc(0)/pad_out 14.880
Route 1 tc(0)_PAD tc(0)/pad_out tc(0)_PAD 0.000
Clock Clock path delay 0.000
+ Clock(routed)
Source Destination Delay (ns)
ClockBlock/dclk_0 clk(0)_PAD 20.469
Type Location Fanout Instance/Net Source Dest Delay (ns)
clockblockcell F(Clock,0) 1 ClockBlock Input Delay ClockBlock/dclk_0 0.000
Route 1 Net_11_local ClockBlock/dclk_0 clk(0)/pin_input 4.974
iocell2 P0[7] 1 clk(0) clk(0)/pin_input clk(0)/pad_out 15.495
Route 1 clk(0)_PAD clk(0)/pad_out clk(0)_PAD 0.000
Clock Clock path delay 0.000
ClockBlock/dclk_0 clk(0)_PAD 20.469
Type Location Fanout Instance/Net Source Dest Delay (ns)
clockblockcell F(Clock,0) 1 ClockBlock Input Delay ClockBlock/dclk_0 0.000
Route 1 Net_11_local ClockBlock/dclk_0 clk(0)/pin_input 4.974
iocell2 P0[7] 1 clk(0) clk(0)/pin_input clk(0)/pad_out 15.495
Route 1 clk(0)_PAD clk(0)/pad_out clk(0)_PAD 0.000
Clock Clock path delay 0.000
+ CyBUS_CLK
Source Destination Delay (ns)
DMA_TX/termout nrq(0)_PAD 26.885
Type Location Fanout Instance/Net Source Dest Delay (ns)
drqcell1 [DrqContainer=(0)][DrqId=(0)] 1 DMA_TX DMA_TX/clock DMA_TX/termout 9.000
Route 1 Net_15 DMA_TX/termout nrq(0)/pin_input 2.862
iocell1 P0[5] 1 nrq(0) nrq(0)/pin_input nrq(0)/pad_out 15.023
Route 1 nrq(0)_PAD nrq(0)/pad_out nrq(0)_PAD 0.000
Clock Clock path delay 0.000
\TopDesign_1:Datapath_1:u0\/f0_bus_stat_comb drq(0)_PAD 25.376
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,4) 1 \TopDesign_1:Datapath_1:u0\ \TopDesign_1:Datapath_1:u0\/busclk \TopDesign_1:Datapath_1:u0\/f0_bus_stat_comb 3.110
Route 1 Net_172 \TopDesign_1:Datapath_1:u0\/f0_bus_stat_comb drq(0)/pin_input 6.705
iocell4 P0[6] 1 drq(0) drq(0)/pin_input drq(0)/pad_out 15.561
Route 1 drq(0)_PAD drq(0)/pad_out drq(0)_PAD 0.000
Clock Clock path delay 0.000